miegl a95cce3d20 rtl: remove inferred CHDR conversion latches ...

Give curr_word a complete combinational assignment and use blocking assignments in chdr_16sc_to_12sc.

This removes the two 64-bit latch banks and the resulting bogus inferred-clock timing endpoints while preserving all legal FSM-state behavior.

2026-08-25 22:36:27 +02:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

rtl: remove inferred CHDR conversion latches

2026-08-25 22:36:27 +02:00

sim

fpga: sim: Make members accessible in RfnocBlockCtrlBfm

2025-04-22 10:04:32 -05:00

tools

fpga: tools: Add assert option to synthesis

2025-04-03 11:01:14 -05:00

top

timing: bound asynchronous GPIF-radio crossings

2026-08-25 22:33:46 +02:00

vivado/b210_k7

fifo: replace synthesized simulation FIFO

2026-08-25 22:21:16 +02:00

.gitignore

vivado: add reproducible 2024.1 project build

2026-08-24 17:50:44 +02:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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