b210-k7-fpga

T

miegl e7b1ac41e0 timing: model SISO and MIMO BUFGMUX clocks

Create generated clock copies on the shared radio BUFGMUX output and mark the full-rate SISO and divide-by-two MIMO modes logically exclusive.

This prevents static timing from attempting impossible cross-mode hold fixes while retaining valid timing relationships outside the shared clock tree.

2026-08-25 22:31:36 +02:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fifo: synchronize read-domain reset handling

2026-08-25 22:22:39 +02:00

sim

fpga: sim: Make members accessible in RfnocBlockCtrlBfm

2025-04-22 10:04:32 -05:00

tools

fpga: tools: Add assert option to synthesis