miegl eb84b6c949 fifo: synchronize read-domain reset handling ...

Synchronize legacy and XPM reset indications into the FIFO read clock domain instead of feeding cross-domain reset logic into asynchronous PRE/CLR paths.

This removes the FIFO-induced CDC-10 findings while preserving legacy reset behavior.

2026-08-25 22:22:39 +02:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fifo: synchronize read-domain reset handling

2026-08-25 22:22:39 +02:00

sim

fpga: sim: Make members accessible in RfnocBlockCtrlBfm

2025-04-22 10:04:32 -05:00

tools

fpga: tools: Add assert option to synthesis

2025-04-03 11:01:14 -05:00

top

b200: import original Kintex-7 clone port

2026-08-23 11:42:22 +02:00

vivado/b210_k7

fifo: replace synthesized simulation FIFO

2026-08-25 22:21:16 +02:00

.gitignore

vivado: add reproducible 2024.1 project build

2026-08-24 17:50:44 +02:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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