Wade Fife 2f5b331f30 fpga: sim: Make members accessible in RfnocBlockCtrlBfm ...

Original-commit: 8493888c67a2a7f34e71ecb764ba0316286881a5

2025-04-22 10:04:32 -05:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fpga: lib: Add initial value to ram_2port

2025-04-09 13:50:17 -05:00

sim

fpga: sim: Make members accessible in RfnocBlockCtrlBfm

2025-04-22 10:04:32 -05:00

tools

fpga: tools: Add assert option to synthesis

2025-04-03 11:01:14 -05:00

top

fpga: x410: Fix NCO reset mechanism

2025-04-17 15:37:13 +02:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%