Wade Fife 6bcbd09a6b fpga: tools: Change -onfinish to final ...

This changes the -onfinish setting from "stop" to "final" for Questa
and ModelSim. The "final" setting is required so that SystemVerilog
final blocks run. This also has the same effect as "stop" in that it
won't ask you in the GUI if you want to exit the simulator when
$finish() is called.


Original-commit: 7ab4e9a4e2c0408ca595ad168199a54bf416c894

2025-03-17 13:40:26 -05:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fpga: rfnoc: fft: Support multiple samples per cycle

2025-03-07 12:39:34 -06:00

sim

fpga: sim: Add coerce function to PkgMath

2025-02-26 22:09:04 -06:00

tools

fpga: tools: Change -onfinish to final

2025-03-17 13:40:26 -05:00

top

fpga: x400: Change NUM_DRAM_BANKS to 2 on X410 X4_400 image

2025-02-27 10:53:07 -06:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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