Wade Fife bb2bfbfe95 fpga: lib: Add AXI-Stream load split and merge modules ...

Original-commit: 32fb626ef1b1d3078fd331143b03cd38d1e155f0

2025-02-14 15:59:19 -06:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fpga: lib: Add AXI-Stream load split and merge modules

2025-02-14 15:59:19 -06:00

sim

rfnoc: lib: introduce ctrl-port interface and BFM

2025-02-14 08:04:26 -06:00

tools

fpga: tools: Refactor viv_ip_xci_editor.py

2025-02-07 14:52:28 +01:00

top

fpga: x440: fix refactored rf_core_full

2025-02-13 07:58:10 -06:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%