Wade Fife c9d2c066f3 fpga: lib: Fix pass-through mode in axi_fifo
A missing "else" after 6ea4e48 was causing two configurations to occur
at the same time for some values of SIZE.

This commit also sets the "space" and "occupied" outputs to 0 when in
pass-through mode.


Original-commit: 19b5c85b514e1c37238308e405108c69ecbddb7e
2025-04-08 12:26:02 -05:00
S
Description
No description provided
84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%