Commit Graph
355 Commits
Author SHA1 Message Date
Wade Fife ddcc0b1211 fpga: tools: Detect check_timing issues during build
Original-commit: 7f13abe9b48b6aedbbfb726732faa16c305be0ac
2022-11-18 14:53:41 -06:00
Wade Fife f16a4c0996 fpga: lib: Fix inferred latch in ep_autonegotiation
Original-commit: 4a011e8c905d8ae7164ac2671177093a2e215842
2022-11-18 14:53:41 -06:00
Wade Fife 91a99b78d6 fpga: rfnoc: Fix inferred latch in chdr_strip_header
Original-commit: 4c7cd12e8cd0f541d4cd824690c163e4558abd51
2022-11-13 16:47:57 -06:00
Wade Fife 7dc93d0e8c fpga: e320 Change MIG arbitration to RD_PRI_REG
Original-commit: 2a27f72f86e74c569e5ea158a5ca9cde68c41a97
2022-11-08 08:20:48 -06:00
Wade Fife 104ae54542 fpga: x300: Change MIG arbitration to RD_PRI_REG
Original-commit: 27ebd95d29ed457ef032604b034b8326da0a20aa
2022-11-08 08:20:48 -06:00
Wade Fife 729aa788af fpga: Require AR76780 for X3xx and E3xx
Patch AR76780 was already listed as a requirement for X4xx and N3xx,
but was not listed as a requirement for X3xx and E3xx. This change
makes it required for all Vivado-based USRPs.


Original-commit: 5aa6bc4418a30d6e6fde80b80632f9f9115ea5c4
2022-09-23 15:09:35 -05:00
Wade Fife 6dad16ccab fpga: Fix Vivado version check in viv_hardware_utils
Original-commit: b5f324f1df7ac3a30c7669efa73e58aaf02e1f78
2022-09-08 11:53:44 -05:00
Wade Fife 5bb61528d9 fpga: x300: Cleanup MTU parameters
Original-commit: c781f753d6bbf1d22621fe905287b7842d986177
2022-09-01 14:41:55 -05:00
Wade Fife 1d9a3018db fpga: n3xx: Cleanup MTU parameters
Original-commit: 9e4c8cbbbb8677eecbab66ab01a02375664ad4a2
2022-09-01 14:41:55 -05:00
Wade Fife 521c7684fc fpga: e320: Cleanup MTU parameters
Original-commit: a6a76002ead284815d9337e30c50f590466eb429
2022-09-01 14:41:55 -05:00
Wade Fife 2f677eddda fpga: e31x: Cleanup MTU parameters
Original-commit: 55a1ef7e50d271459f44b98d55860bfb2bbe2d19
2022-09-01 14:41:55 -05:00
Wade Fife 919acb248f fpga: lib: Add MTU parameter to eth_internal
Original-commit: 2745b6c01b75ae4480a38f91b9601c231ce1ea72
2022-09-01 14:41:55 -05:00
Wade Fife 354b59e430 fpga: n3xx: Add PROTOVER to n3xx_mgt_wrapper
Original-commit: 936965c104696b7883674a713d457042eaeb249f
2022-09-01 14:41:55 -05:00
Wade Fife 21091fb07c fpga: e31x: Add PROTOVER to eth_internal
Original-commit: 4d85a77d5f1a97020a7ad7d06a1ce75d94964309
2022-09-01 14:41:55 -05:00
Wade Fife 92abd3945a fpga: n3xx: Remove unused USE_REPLAY parameter
Original-commit: 244b0a575fce2eb9e489b7f46c6e6cd13ec7a0bd
2022-09-01 14:41:55 -05:00
Wade Fife 82739c1dae fpga: lib: Add eth_ipv4_interface_tb
Original-commit: 4f9a71f12204728446723f171d4cf0edcbf5027a
2022-08-29 17:01:45 -05:00
Wade Fife 2a74e8cd67 fpga: lib: Add RegPort SystemVerilog interface
Original-commit: d628c136a0cca7dddc47711f86f52f2c9e2ca089
2022-08-29 17:01:45 -05:00
Wade Fife c09489b6b0 fpga: sim: Support unused tkeep in AxiStreamPacket::dump_bytes()
Original-commit: 0af84329a7d0f8c97131e14a522a2e0939dbb951
2022-08-29 17:01:45 -05:00
Wade Fife a23ff16c07 fpga: n3xx: Bump FPGA compat to 8.1
Original-commit: 65671437c81fe0395dd2400a1e36bbc5fd934b40
2022-08-29 17:01:45 -05:00
Wade Fife e087a3c12b fpga: e320: Bump FPGA compat to 6.1
Original-commit: 50949d28d47100aea4ebc0563f6c1092a3b9b57e
2022-08-29 17:01:45 -05:00
Wade Fife 20340f7054 fpga: lib: Add compat to Verilog transport adapter
Original-commit: e716c8c720718f69d39823b722f5e013df99a3d5
2022-08-29 17:01:45 -05:00
Wade Fife 5f4d53eacb fpga: e320: Support advanced transport adapter
- Fix NODE_INST
- Fix RFNOC_PROTOVER
- Add option to use SystemVerilog transport adapter for raw UDP


Original-commit: 0114e108af63d9ac785649c8099a042299624943
2022-08-29 17:01:45 -05:00
Wade Fife a270cb29d6 fpga: n3xx: Support advanced transport adapter
- Fix NODE_INST
- Fix RFNOC_PROTOVER
- Add option to use SystemVerilog transport adapter for raw UDP


Original-commit: 693ec2c896306bcba3686385e5861593040d4cbd
2022-08-29 17:01:45 -05:00
Wade Fife 6981891978 fpga: lib: Add verilog-compatible wrapper for eth_ipv4_interface
Original-commit: 7052a4f02bb5cab0a2ee7339af5f1e15da087a7b
2022-08-29 17:01:45 -05:00
Wade Fife 257e5b4db9 fpga: x400: Bump FPGA compat to 7.9
Original-commit: 910dd82599ff192523e04061582cbafb4394e207
2022-08-29 17:01:45 -05:00
Wade FifeandMartin Braun f2b4426b0f fpga: lib: Add advanced features to IPv4 SV transport adapter
This adds several features to the SystemVerilog Eth/IPv4/UDP transport
adaptor including:

- Compat register
- NODE_INST register
- Capabilities register
- KV map access for custom routing on RX data paths
- CHDR header removal for raw payloads to be sent over UDP

Also adds xport_adapter_ctrl.py, which allows controlling the new
registers.

Co-authored-by: Martin Braun <martin.braun@ettus.com>


Original-commit: 3c3da4c62f33d02bb05bcdc38e8929cbf2cdd9a3
2022-08-29 17:01:45 -05:00
Wade Fife cad2f7ba5c fpga: lib: Add support for length in tuser in eth_ipv4_add_udp
Original-commit: 672487634ef817026fad83d48d3c341f80fa4d46
2022-08-29 17:01:45 -05:00
Wade Fife dce09f8fd7 fpga: lib: Add chdr_strip_header module
Original-commit: 4bf988aa3c9aa3885dc30e3da7ea67fcec48c97e
2022-08-29 17:01:45 -05:00
Wade Fife 16587514ba fpga: x400: Fix transport adapter PROTOVER
Original-commit: 7b93c4a37abc91b6607a3401e39605bc23cae69f
2022-08-29 17:01:45 -05:00
Wade Fife 5af17e0984 fpga: x400: Fix NODE_INST for transport adapters
Set the NODE_INST parameter for each transport adapter on X4xx so that
each adapter has a unique node instance number.


Original-commit: 8e87a4d24aeeb77a9528ff67a36d8a0ae12e7137
2022-08-29 17:01:45 -05:00
Wade Fife 1756797ec2 fpga: lib: Fix NODE_INST parameter in eth_internal
The NODE_INST parameter was set to 0. This adds it as a parameter so
that each transport adapter can have a unique node instance number.


Original-commit: c6bfd2e7f8313d727c2e557958f1b1ac2f674d98
2022-08-29 17:01:45 -05:00
Wade Fife 032b9677aa fpga: lib: Add NET_CHDR_W parameter to transport adapters
The NET_CHDR_W parameter tells the transport adapter what CHDR width
is used in transport packets, such as Ethernet packets. By default the
CHDR width used by the transport and RFNoC core will be the same. The
NET_CHDR_W parameter can be used in situations where the RFNoC core
expects a CHDR width from the transport adapter that is different from
that used over the network. In this situation, the transport adapter
will rewrite the CHDR packets so that each side gets the expected CHDR
width.


Original-commit: a9e49b7c587ef778ee0fe327e8bdcb15e0b0fc95
2022-08-29 17:01:45 -05:00
Wade Fife f010ce051e fpga: Fix target dependencies in Makefile.xxx.inc
Original-commit: e0147fd19347e4e2b2ec1cae193d4c295b9c427b
2022-08-29 07:53:32 -05:00
Wade Fife ea58284d4d fpga: e31x: Fix IP dependencies
- Split SG1 and SG3 IP targets
- Remove non-existent "RFNOC" targets


Original-commit: 8320adbc18455a360d4bd26798d1f435701172b9
2022-08-29 07:53:32 -05:00
Humberto Jimenez 5f2dd66658 fpga: n3xx: Add BUFG to SPI output line to ease timing
Vivado has demonstrated difficulty meeting timing with the spi0_mosi split. To
improve the chances of meeting timing, we are routing this signal through a
BUFG. This makes the routing step use a more efficient net routing that eases
timing closure.


Original-commit: 8c49730e4cf6af172d26ee6a5d35182ed3160058
2022-08-25 13:55:30 -05:00
Humberto Jimenez fb83fe3830 fpga: sim: Workaround Vivado bug in ChdrIfaceBfm_tb
Original-commit: 9e4de0d0b7a1a35a5b3220a605c329e60f8b5e83
2022-08-25 13:55:30 -05:00
Wade Fife 3fc345d3ae fpga: sim: Update struct enum initialization
In Vivado 2021.1, it is no longer allowed to use "default: 0" to
initialize an enum within a packed struct. So we must initalize enum
data members explicitly now.


Original-commit: 8007b6b4dff5b64d476b2e3ccb68a777c2f02c8b
2022-08-25 13:55:30 -05:00
Wade Fife dd1e980463 fpga: lib: Fix addsub_hls
Original-commit: f3e28c36a0e37341038370856ab2babd1dff0b3b
2022-08-25 13:55:30 -05:00
Humberto Jimenez b6d9977685 fpga: Use AR76780 patch for fir_compiler
Original-commit: 719cccea7fd6a8a27d6cb96242984240c583a2ee
2022-08-25 13:55:30 -05:00
Wade Fife 31c638f98c fpga: x400: Fix link status detection of 10 GbE IP
This fixes some issues with the 2021.1 version of the 10 GbE IP. In the
new version, link status is sporadically detected by the Xilinx IP when
nothing is connected to the port. Also, when the SFP is inserted, the
link status goes up and down multiple times. This change fixes this by
adding a counter and only considering it "linked" when the link has
been stable for some amount of time.


Original-commit: 846c7be2e42f1db6d7c7cc0b1128e014f83e3bae
2022-08-25 13:55:30 -05:00
Sam O'Brien 1b952d33df fpga: x400: Upgrade to Vivado 2021.1
Commit includes:
- Upgrade x400-specific IP
- Removal of xge_pcs_pma IP patch


Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
2022-08-25 13:55:30 -05:00
Sam O'Brien 6193c765fe fpga: x300: Upgrade to Vivado 2021.1
Original-commit: 629cee33d919ef8a0b742790f5fcc642b392abcd
2022-08-25 13:55:30 -05:00
Sam O'Brien 2997319b47 fpga: n3xx: Fix async clocks relationship
Original-commit: 9774025b1e0769da31277c97461b442a21df51b4
2022-08-25 13:55:30 -05:00
Sam O'Brien 931bd6491a fpga: n3xx: Upgrade to Vivado 2021.1
Original-commit: c9886751dc361e44345a61e9b8bed310c3d8a9c2
2022-08-25 13:55:30 -05:00
Sam O'Brien c41bd8f72b fpga: e320: Upgrade to Vivado 2021.1
Original-commit: 1f57d67c4ceadbb19ce203ee9ad9e46f612c0a76
2022-08-25 13:55:30 -05:00
Sam O'Brien 0bb7d1dd93 fpga: e31x: Upgrade to Vivado 2021.1
Original-commit: 77f921c7c5d06095af5eb86a209348251edef07d
2022-08-25 13:55:30 -05:00
Sam O'Brien a63c80bd23 fpga: lib: Upgrade to Vivado 2021.1
Original-commit: b0dc0faed1eceef3ba28ce03555658fca2423c46
2022-08-25 13:55:30 -05:00
Humberto Jimenez f53e3f27fc fpga: tools: Fix HLS IP builder for Vivado 2021.1
Original-commit: 9300a0718274ede56cda3f48e43c9f0e1df4674b
2022-08-25 13:55:30 -05:00
Sam O'Brien 959ce49389 fpga: tools: Allow IP renaming with viv_ip_xci_editor.py
Original-commit: e74f56b95a5ba8359468f2c4770e828731b8e1ef
2022-08-25 13:55:30 -05:00
Sam O'Brien 187c81719b fpga: tools: Add utility to upgrade TCL-based BD
Original-commit: a99bed698576c1e0ab6c6c6aae68d5da75e6bd75
2022-08-25 13:55:30 -05:00