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Humberto Jimenez 5f2dd66658 fpga: n3xx: Add BUFG to SPI output line to ease timing 
Vivado has demonstrated difficulty meeting timing with the spi0_mosi split. To
improve the chances of meeting timing, we are routing this signal through a
BUFG. This makes the routing step use a more efficient net routing that eases
timing closure.


Original-commit: 8c49730e4cf6af172d26ee6a5d35182ed3160058
2022-08-25 13:55:30 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: sim: Update struct enum initialization
2022-08-25 13:55:30 -05:00
sim
fpga: sim: Workaround Vivado bug in ChdrIfaceBfm_tb
2022-08-25 13:55:30 -05:00
tools
fpga: tools: Fix HLS IP builder for Vivado 2021.1
2022-08-25 13:55:30 -05:00
top
fpga: n3xx: Add BUFG to SPI output line to ease timing
2022-08-25 13:55:30 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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