b210-k7-fpga

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Humberto Jimenez 5f2dd66658 fpga: n3xx: Add BUFG to SPI output line to ease timing

Vivado has demonstrated difficulty meeting timing with the spi0_mosi split. To
improve the chances of meeting timing, we are routing this signal through a
BUFG. This makes the routing step use a more efficient net routing that eases
timing closure.


Original-commit: 8c49730e4cf6af172d26ee6a5d35182ed3160058

2022-08-25 13:55:30 -05:00

b2xxmini

fpga: b2xx: Generate utilization report files

2022-02-10 11:35:47 -07:00

b200

fpga: b2xx: Generate utilization report files

2022-02-10 11:35:47 -07:00

e31x

fpga: e31x: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

e320

fpga: e320: Upgrade to Vivado 2021.1