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b210-k7-fpga/top/n3xx
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Humberto Jimenez 5f2dd66658 fpga: n3xx: Add BUFG to SPI output line to ease timing 
Vivado has demonstrated difficulty meeting timing with the spi0_mosi split. To
improve the chances of meeting timing, we are routing this signal through a
BUFG. This makes the routing step use a more efficient net routing that eases
timing closure.


Original-commit: 8c49730e4cf6af172d26ee6a5d35182ed3160058
2022-08-25 13:55:30 -05:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dboards
fpga: n3xx: Add BUFG to SPI output line to ease timing
2022-08-25 13:55:30 -05:00
doc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dts
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
ip
fpga: Use AR76780 patch for fir_compiler
2022-08-25 13:55:30 -05:00
sim
fpga: n3xx: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_n3xx.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: Update makefiles to allow parallel FPGA builds
2022-08-16 10:16:22 -05:00
Makefile.n3xx.inc
fpga: Update makefiles to allow parallel FPGA builds
2022-08-16 10:16:22 -05:00
mb_clocks.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_timing.xdc
fpga: n3xx: Fix async clocks relationship
2022-08-25 13:55:30 -05:00
n3xx_clocking.v
fpga: n3xx: Fix clock frequency comments
2022-03-26 21:52:26 -05:00
n3xx_core.v
fpga: Use PROTOVER and CHDR_W from RFNoC image builder
2022-03-29 14:45:04 -05:00
n3xx_db_fe_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_channel_wrapper.v
N3xx: Fix White Rabbit
2021-08-04 15:19:58 -05:00
n3xx_mgt_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_wrapper.v
fpga: n3xx: Fix White Rabbit images
2020-07-01 15:49:13 -05:00
n3xx_serial_dac_arb.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_serial_dac.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr_top.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_bist_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_bist_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_bist_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n300_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n310_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_bist_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_bist_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_bist_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n310_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n320_bist_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_bist_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_bist_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n320_bist_static_router.hex
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n320_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
setupenv.sh
fpga: Use AR76780 patch for fir_compiler
2022-08-25 13:55:30 -05:00
WrapBufg.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00