Humberto Jimenez 5f2dd66658 fpga: n3xx: Add BUFG to SPI output line to ease timing ...

Vivado has demonstrated difficulty meeting timing with the spi0_mosi split. To
improve the chances of meeting timing, we are routing this signal through a
BUFG. This makes the routing step use a more efficient net routing that eases
timing closure.


Original-commit: 8c49730e4cf6af172d26ee6a5d35182ed3160058

2022-08-25 13:55:30 -05:00

..

common

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

mg

fpga: n3xx: Add BUFG to SPI output line to ease timing

2022-08-25 13:55:30 -05:00

rh

fpga: Use PROTOVER and CHDR_W from RFNoC image builder

2022-03-29 14:45:04 -05:00