fpga: x400: Upgrade to Vivado 2021.1
Commit includes: - Upgrade x400-specific IP - Removal of xge_pcs_pma IP patch Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
This commit is contained in:
Sam O'Brien
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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@@ -83,10 +83,10 @@ if { ${design_name} eq "" } {
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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@@ -107,11 +107,11 @@ if { ${design_name} eq "" } {
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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@@ -119,10 +119,10 @@ if { ${design_name} eq "" } {
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# Add USER_COMMENTS on $design_name
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set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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@@ -139,7 +139,7 @@ xilinx.com:ip:fir_compiler:7.2\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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@@ -149,7 +149,7 @@ xilinx.com:ip:fir_compiler:7.2\
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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@@ -168,7 +168,7 @@ scale_2x\
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"
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set list_mods_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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foreach mod_vlnv $list_check_mods {
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if { [can_resolve_reference $mod_vlnv] == 0 } {
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@@ -177,14 +177,14 @@ scale_2x\
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}
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if { $list_mods_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
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catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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@@ -208,14 +208,14 @@ proc create_root_design { parentCell } {
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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@@ -263,34 +263,29 @@ proc create_root_design { parentCell } {
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# Create ports
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set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ]
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set data_clk [ create_bd_port -dir I -type clk data_clk ]
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set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {adc_data_out} \
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CONFIG.FREQ_HZ {122880000} \
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] $data_clk
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set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ]
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set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ]
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set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
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set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
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set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {adc_i_data_in:adc_q_data_in} \
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CONFIG.ASSOCIATED_RESET {adc_gearbox_resetn_rclk:rfdc_adc_axi_resetn_rclk} \
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CONFIG.FREQ_HZ {184320000} \
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] $rfdc_clk
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set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {368640000} \
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] $rfdc_clk_2x
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set rfdc_clk_2x [ create_bd_port -dir I -type clk -freq_hz 368640000 rfdc_clk_2x ]
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set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ]
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# Create instance: adc_3_1_clk_converter_0, and set properties
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set block_name adc_3_1_clk_converter
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set block_cell_name adc_3_1_clk_converter_0
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if { [catch {set adc_3_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $adc_3_1_clk_converter_0 eq "" } {
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catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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@@ -306,10 +301,10 @@ proc create_root_design { parentCell } {
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set block_name adc_gearbox_2x1
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set block_cell_name adc_gearbox_2x1_0
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if { [catch {set adc_gearbox_2x1_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $adc_gearbox_2x1_0 eq "" } {
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catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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@@ -334,10 +329,10 @@ proc create_root_design { parentCell } {
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set block_name ddc_saturate
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set block_cell_name ddc_saturate
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if { [catch {set ddc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $ddc_saturate eq "" } {
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catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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@@ -345,7 +340,7 @@ proc create_root_design { parentCell } {
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set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ]
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set_property -dict [ list \
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CONFIG.Clock_Frequency {384} \
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CONFIG.CoefficientVector {-2,0,8,12,0,-26,-36,0,63,81,0,-130,-161,0,241,291,0,-415,-491,0,676,788,0,-1059,-1223,0,1621,1864,0,-2473,-2860,0,3892,4607,0,-6820,-8705,0,17900,36048,43690,36048,17900,0,-8705,-6820,0,4607,3892,0,-2860,-2473,0,1864,1621,0,-1223,-1059,0,788,676,0,-491,-415,0,291,241,0,-161,-130,0,81,63,0,-36,-26,0,12,8,0,-2} \
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CONFIG.CoefficientVector {-2,0,8,12,0,-26,-36,0,63,81,0,-130,-161,0,241,291,0,-415,-491,0,676,788,0,-1059,-1223,0,1621,1864,0,-2473,-2860,0,3892,4607,0,-6820,-8705,0,17900,36048,43690,36048,17900,0,-8705,-6820,0,4607,3892,0,-2860,-2473,0,1864,1621,0,-1223,-1059,0,788,676,0,-491,-415,0,291,241,0,-161,-130,0,81,63,0,-36,-26,0,12,8,0,-2}\
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CONFIG.Coefficient_Fractional_Bits {0} \
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CONFIG.Coefficient_Sets {1} \
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CONFIG.Coefficient_Sign {Signed} \
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@@ -376,10 +371,10 @@ proc create_root_design { parentCell } {
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set block_name scale_2x
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set block_cell_name scale_2x_0
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if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $scale_2x_0 eq "" } {
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catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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set_property -dict [ list \
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@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2019.1
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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@@ -83,10 +83,10 @@ if { ${design_name} eq "" } {
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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@@ -107,11 +107,11 @@ if { ${design_name} eq "" } {
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
|
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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@@ -119,10 +119,10 @@ if { ${design_name} eq "" } {
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# Add USER_COMMENTS on $design_name
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set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name]
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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||||
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||||
if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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||||
return $nRet
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||||
}
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||||
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||||
@@ -139,7 +139,7 @@ xilinx.com:ip:fir_compiler:7.2\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
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||||
foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -149,7 +149,7 @@ xilinx.com:ip:fir_compiler:7.2\
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
@@ -168,7 +168,7 @@ scale_2x\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
@@ -177,14 +177,14 @@ scale_2x\
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -208,14 +208,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -263,22 +263,17 @@ proc create_root_design { parentCell } {
|
||||
|
||||
# Create ports
|
||||
set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ]
|
||||
set data_clk [ create_bd_port -dir I -type clk data_clk ]
|
||||
set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {adc_data_out_resetn_dclk} \
|
||||
CONFIG.FREQ_HZ {122880000} \
|
||||
] $data_clk
|
||||
set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ]
|
||||
set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ]
|
||||
set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ]
|
||||
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {184320000} \
|
||||
] $rfdc_clk
|
||||
set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ]
|
||||
set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ]
|
||||
set rfdc_clk_2x [ create_bd_port -dir I -type clk -freq_hz 368640000 rfdc_clk_2x ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {fir_resetn_rclk2x} \
|
||||
CONFIG.FREQ_HZ {368640000} \
|
||||
] $rfdc_clk_2x
|
||||
set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ]
|
||||
|
||||
@@ -294,10 +289,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name adc_gearbox_2x4
|
||||
set block_cell_name adc_gearbox_2x4_0
|
||||
if { [catch {set adc_gearbox_2x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $adc_gearbox_2x4_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -305,10 +300,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name adc_gearbox_8x4
|
||||
set block_cell_name adc_gearbox_8x4_0
|
||||
if { [catch {set adc_gearbox_8x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $adc_gearbox_8x4_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -333,10 +328,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name ddc_400m_saturate
|
||||
set block_cell_name ddc_400m_saturate_0
|
||||
if { [catch {set ddc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $ddc_400m_saturate_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -344,13 +339,13 @@ proc create_root_design { parentCell } {
|
||||
set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.Clock_Frequency {384} \
|
||||
CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2} \
|
||||
CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2}\
|
||||
CONFIG.Coefficient_Fractional_Bits {0} \
|
||||
CONFIG.Coefficient_Sets {1} \
|
||||
CONFIG.Coefficient_Sign {Signed} \
|
||||
CONFIG.Coefficient_Structure {Inferred} \
|
||||
CONFIG.Coefficient_Width {18} \
|
||||
CONFIG.ColumnConfig {26} \
|
||||
CONFIG.ColumnConfig {13} \
|
||||
CONFIG.Decimation_Rate {3} \
|
||||
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
|
||||
CONFIG.Filter_Type {Decimation} \
|
||||
@@ -372,10 +367,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name scale_2x
|
||||
set block_cell_name scale_2x_0
|
||||
if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $scale_2x_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
set_property -dict [ list \
|
||||
|
||||
@@ -13,13 +13,15 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -43,7 +45,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -59,7 +61,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -68,12 +70,14 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -98,7 +102,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -114,7 +118,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -123,8 +127,9 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
@@ -509,12 +514,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@@ -577,6 +582,22 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TKEEP_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.TSTRB_WIDTH" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"axis_rd_data_count":[{"direction":"out","physical_left":"9","physical_right":"0","is_vector":"true"}],"axis_wr_data_count":[{"direction":"out","physical_left":"9","physical_right":"0","is_vector":"true"}],"m_aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axis_tdata":[{"direction":"out","physical_left":"63","physical_right":"0","is_vector":"true"}],"m_axis_tlast":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axis_tready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axis_tuser":[{"direction":"out","physical_left":"3","physical_right":"0","is_vector":"true"}],"m_axis_tvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s
|
||||
_axis_tdata":[{"direction":"in","physical_left":"63","physical_right":"0","is_vector":"true"}],"s_axis_tlast":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axis_tready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axis_tuser":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"s_axis_tvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"M_AXIS":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"master","parameters":{"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":f
|
||||
alse}],"HAS_TKEEP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TLAST":[{"value":"1","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TREADY":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TSTRB":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"LAYERED_METADATA":[{"value":"undef","value_src":"default","value_permission":
|
||||
"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDATA_NUM_BYTES":[{"value":"8","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDEST_WIDTH":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TID_WIDTH":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TUSER_WIDTH":[{"value":"4","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":t
|
||||
rue,"is_static_object":false}]},"port_maps":{"TDATA":[{"physical_name":"m_axis_tdata","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}],"TDEST":[{"physical_name":"m_axis_tdest","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TID":[{"physical_name":"m_axis_tid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TKEEP":[{"physical_name":"m_axis_tkeep","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"TLAST":[{"physical_name":"m_axis_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TREADY":[{"physical_name":"m_axis_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TSTRB":[{"physical_name":"m_axis_tstrb","physical_left":"7","physical_r
|
||||
ight":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"TUSER":[{"physical_name":"m_axis_tuser","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"TVALID":[{"physical_name":"m_axis_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"S_AXIS":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"slave","parameters":{"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TKEEP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usa
|
||||
ge":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TLAST":[{"value":"1","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TREADY":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TSTRB":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"LAYERED_METADATA":[{"value":"undef","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"
|
||||
value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDATA_NUM_BYTES":[{"value":"8","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDEST_WIDTH":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TID_WIDTH":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TUSER_WIDTH":[{"value":"4","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"TDATA":[{"physical_name":"s_axis_tdata","physical_left":"63","physical_right":"0",
|
||||
"logical_left":"63","logical_right":"0","port_maps_used":"none"}],"TDEST":[{"physical_name":"s_axis_tdest","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TID":[{"physical_name":"s_axis_tid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TKEEP":[{"physical_name":"s_axis_tkeep","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"TLAST":[{"physical_name":"s_axis_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TREADY":[{"physical_name":"s_axis_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TSTRB":[{"physical_name":"s_axis_tstrb","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"TUSER":[{"physical_name":"s_axis_tuser","physical_le
|
||||
ft":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"TVALID":[{"physical_name":"s_axis_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"master_aclk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"M_AXIS:M_AXI","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":
|
||||
"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"m_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"slave_aclk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BU
|
||||
SIF":[{"value":"S_AXIS:S_AXI","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"s_aresetn","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_
|
||||
permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"s_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"slave_aresetn":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"
|
||||
RST":[{"physical_name":"s_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -128,7 +128,7 @@ xilinx.com:ip:smartconnect:1.0\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -138,14 +138,14 @@ xilinx.com:ip:smartconnect:1.0\
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -169,14 +169,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -252,11 +252,10 @@ proc create_root_design { parentCell } {
|
||||
|
||||
|
||||
# Create ports
|
||||
set clk40 [ create_bd_port -dir I -type clk clk40 ]
|
||||
set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {e2c:axi_eth_dma:axi_hp:c2e} \
|
||||
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $clk40
|
||||
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
|
||||
set eth_rx_irq [ create_bd_port -dir O -type intr eth_rx_irq ]
|
||||
@@ -301,10 +300,10 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_eth_dma/axi_resetn] [get_bd_pins smartconnect_eth_dma/aresetn]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_SG] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
|
||||
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_MM2S] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
|
||||
create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_S2MM] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg
|
||||
create_bd_addr_seg -range 0x010000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma] [get_bd_addr_segs axi_eth_dma/S_AXI_LITE/Reg] SEG_axi_eth_dma_Reg
|
||||
assign_bd_address -offset 0x00000000 -range 0x001000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma/Data_SG] [get_bd_addr_segs axi_hp/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x001000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma/Data_MM2S] [get_bd_addr_segs axi_hp/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x001000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma/Data_S2MM] [get_bd_addr_segs axi_hp/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x010000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma] [get_bd_addr_segs axi_eth_dma/S_AXI_LITE/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } {
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } {
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -167,14 +167,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -264,21 +264,19 @@ proc create_root_design { parentCell } {
|
||||
|
||||
|
||||
# Create ports
|
||||
set M0_AXI_ACLK [ create_bd_port -dir I -type clk M0_AXI_ACLK ]
|
||||
set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
|
||||
CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
|
||||
CONFIG.FREQ_HZ {350000000} \
|
||||
] $M0_AXI_ACLK
|
||||
set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $M0_AXI_ARESETN
|
||||
set S0_AXI_ACLK [ create_bd_port -dir I -type clk S0_AXI_ACLK ]
|
||||
set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \
|
||||
CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN:S0_AXI_ARESETN} \
|
||||
CONFIG.FREQ_HZ {350000000} \
|
||||
] $S0_AXI_ACLK
|
||||
set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
|
||||
|
||||
@@ -307,8 +305,8 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -100,11 +100,11 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
@@ -113,10 +113,10 @@ if { ${design_name} eq "" } {
|
||||
set_property USER_COMMENTS.comment_0 "Note 1: The ID width of the AXI interconnect (xbar) master changes depending on the axi_interconnect optimization strategy. It will be zero for 'minimize area' and non-zero for 'maximize performance'.
|
||||
Note 2: I have explicitly set ID width to 1 on the input ports to match our AXI master and to 4 on the output block to match the DRAM slave." [get_bd_designs $design_name]
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -133,7 +133,7 @@ xilinx.com:ip:axi_register_slice:2.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -143,14 +143,14 @@ xilinx.com:ip:axi_register_slice:2.1\
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -174,14 +174,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -226,7 +226,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PHASE {0.000} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
@@ -259,7 +258,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PHASE {0.000} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
@@ -292,7 +290,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PHASE {0.000} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
@@ -325,7 +322,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.NUM_READ_THREADS {1} \
|
||||
CONFIG.NUM_WRITE_OUTSTANDING {2} \
|
||||
CONFIG.NUM_WRITE_THREADS {1} \
|
||||
CONFIG.PHASE {0.000} \
|
||||
CONFIG.PROTOCOL {AXI4} \
|
||||
CONFIG.READ_WRITE_MODE {READ_WRITE} \
|
||||
CONFIG.RUSER_BITS_PER_BYTE {0} \
|
||||
@@ -337,21 +333,19 @@ proc create_root_design { parentCell } {
|
||||
|
||||
|
||||
# Create ports
|
||||
set M0_AXI_ACLK [ create_bd_port -dir I -type clk M0_AXI_ACLK ]
|
||||
set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {M0_AXI} \
|
||||
CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \
|
||||
CONFIG.FREQ_HZ {350000000} \
|
||||
] $M0_AXI_ACLK
|
||||
set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $M0_AXI_ARESETN
|
||||
set S0_AXI_ACLK [ create_bd_port -dir I -type clk S0_AXI_ACLK ]
|
||||
set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI:S2_AXI:S3_AXI} \
|
||||
CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \
|
||||
CONFIG.FREQ_HZ {350000000} \
|
||||
] $S0_AXI_ACLK
|
||||
set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ]
|
||||
|
||||
@@ -360,6 +354,276 @@ proc create_root_design { parentCell } {
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {256} \
|
||||
CONFIG.ID_WIDTH {4} \
|
||||
CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A00_ADDR_WIDTH {0} \
|
||||
CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \
|
||||
CONFIG.NUM_MI {1} \
|
||||
CONFIG.NUM_SI {4} \
|
||||
CONFIG.S01_BASE_ID {0x00000004} \
|
||||
@@ -549,10 +813,10 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_4/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins axi_register_slice_4/aresetn] [get_bd_pins axi_register_slice_5/aresetn] [get_bd_pins axi_register_slice_6/aresetn] [get_bd_pins axi_register_slice_7/aresetn] [get_bd_pins axi_register_slice_8/aresetn]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M0_AXI_Reg
|
||||
create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M0_AXI_Reg
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } {
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } {
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -167,14 +167,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -189,7 +189,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -206,7 +205,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_qsfp1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -227,7 +225,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
@@ -256,12 +253,11 @@ proc create_root_design { parentCell } {
|
||||
|
||||
|
||||
# Create ports
|
||||
set clk40 [ create_bd_port -dir I -type clk clk40 ]
|
||||
set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {m_axi_qsfp0:m_axi_qsfp1:s_axi_app} \
|
||||
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $clk40
|
||||
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
|
||||
|
||||
@@ -281,8 +277,8 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x001200000000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp0/Reg] SEG_m_axi_qsfp0_Reg
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x001200040000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp1/Reg] SEG_m_axi_qsfp1_Reg
|
||||
assign_bd_address -offset 0x001200000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp0/Reg] -force
|
||||
assign_bd_address -offset 0x001200040000 -range 0x00040000 -target_address_space [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp1/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } {
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } {
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -167,14 +167,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -189,7 +189,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_hp ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {49} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {128} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {1} \
|
||||
@@ -210,7 +209,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {128} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
@@ -243,7 +241,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {128} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
@@ -276,7 +273,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {128} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
@@ -309,7 +305,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {128} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
@@ -338,12 +333,11 @@ proc create_root_design { parentCell } {
|
||||
|
||||
|
||||
# Create ports
|
||||
set clk40 [ create_bd_port -dir I -type clk clk40 ]
|
||||
set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {s_axi_hp_dma0:s_axi_hp_dma1:s_axi_hp_dma2:s_axi_hp_dma3:m_axi_hp} \
|
||||
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $clk40
|
||||
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
|
||||
|
||||
@@ -381,10 +375,10 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_interconnect_0/S03_ARESETN]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma0] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
|
||||
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma1] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
|
||||
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma2] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
|
||||
create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma3] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg
|
||||
assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma0] [get_bd_addr_segs m_axi_hp/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma1] [get_bd_addr_segs m_axi_hp/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma2] [get_bd_addr_segs m_axi_hp/Reg] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma3] [get_bd_addr_segs m_axi_hp/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } {
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } {
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -167,14 +167,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -189,7 +189,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_dma0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -203,7 +202,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_dma1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -217,7 +215,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_dma2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -231,7 +228,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_dma3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma3 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -245,7 +241,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_mac0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -262,7 +257,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_mac1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -276,7 +270,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_mac2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -290,7 +283,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_mac3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac3 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -304,7 +296,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_misc0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -321,7 +312,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_misc1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc1 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -335,7 +325,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_misc2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc2 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -349,7 +338,6 @@ proc create_root_design { parentCell } {
|
||||
set m_axi_misc3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc3 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADDR_WIDTH {40} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BURST {0} \
|
||||
@@ -366,7 +354,6 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.ARUSER_WIDTH {0} \
|
||||
CONFIG.AWUSER_WIDTH {0} \
|
||||
CONFIG.BUSER_WIDTH {0} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.DATA_WIDTH {32} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.HAS_BRESP {1} \
|
||||
@@ -395,12 +382,11 @@ proc create_root_design { parentCell } {
|
||||
|
||||
|
||||
# Create ports
|
||||
set clk40 [ create_bd_port -dir I -type clk clk40 ]
|
||||
set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {m_axi_misc0:m_axi_mac0:s_axi_eth:m_axi_misc3:m_axi_mac3:m_axi_dma1:m_axi_misc1:m_axi_mac2:m_axi_dma2:m_axi_mac1:m_axi_misc2:m_axi_dma0:m_axi_dma3} \
|
||||
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
|
||||
CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $clk40
|
||||
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
|
||||
|
||||
@@ -430,18 +416,18 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] SEG_m_axi_dma0_Reg
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00010000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] SEG_m_axi_dma1_Reg
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00020000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] SEG_m_axi_dma2_Reg
|
||||
create_bd_addr_seg -range 0x00008000 -offset 0x00030000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] SEG_m_axi_dma3_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0000C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] SEG_m_axi_mac0_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0001C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] SEG_m_axi_mac1_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0002C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] SEG_m_axi_mac2_Reg
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x0003C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] SEG_m_axi_mac3_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00008000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] SEG_m_axi_misc0_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00018000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] SEG_m_axi_misc1_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00028000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] SEG_m_axi_misc2_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x00038000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] SEG_m_axi_misc3_Reg
|
||||
assign_bd_address -offset 0x00000000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] -force
|
||||
assign_bd_address -offset 0x00010000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] -force
|
||||
assign_bd_address -offset 0x00020000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] -force
|
||||
assign_bd_address -offset 0x00030000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] -force
|
||||
assign_bd_address -offset 0x0000C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] -force
|
||||
assign_bd_address -offset 0x0001C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] -force
|
||||
assign_bd_address -offset 0x0002C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] -force
|
||||
assign_bd_address -offset 0x0003C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] -force
|
||||
assign_bd_address -offset 0x00008000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] -force
|
||||
assign_bd_address -offset 0x00018000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] -force
|
||||
assign_bd_address -offset 0x00028000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] -force
|
||||
assign_bd_address -offset 0x00038000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -83,10 +83,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -107,19 +107,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -137,7 +137,7 @@ xilinx.com:ip:axis_register_slice:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -147,7 +147,7 @@ xilinx.com:ip:axis_register_slice:1.1\
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
@@ -165,7 +165,7 @@ duc_saturate\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
@@ -174,14 +174,14 @@ duc_saturate\
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -205,14 +205,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -248,22 +248,19 @@ proc create_root_design { parentCell } {
|
||||
set dac_data_in_resetn_dclk [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk ]
|
||||
set dac_data_in_resetn_rclk [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk ]
|
||||
set dac_data_in_resetn_rclk2x [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk2x ]
|
||||
set data_clk [ create_bd_port -dir I -type clk data_clk ]
|
||||
set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {dac_data_in} \
|
||||
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk} \
|
||||
CONFIG.FREQ_HZ {122880000} \
|
||||
] $data_clk
|
||||
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
|
||||
set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {dac_data_out} \
|
||||
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk} \
|
||||
CONFIG.FREQ_HZ {184320000} \
|
||||
] $rfdc_clk
|
||||
set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ]
|
||||
set rfdc_clk_2x [ create_bd_port -dir I -type clk -freq_hz 368640000 rfdc_clk_2x ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk2x} \
|
||||
CONFIG.FREQ_HZ {368640000} \
|
||||
] $rfdc_clk_2x
|
||||
|
||||
# Create instance: constant_high, and set properties
|
||||
@@ -273,10 +270,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name dac_1_3_clk_converter
|
||||
set block_cell_name dac_1_3_clk_converter_0
|
||||
if { [catch {set dac_1_3_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $dac_1_3_clk_converter_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -284,10 +281,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name dac_2_1_clk_converter
|
||||
set block_cell_name dac_2_1_clk_converter_0
|
||||
if { [catch {set dac_2_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $dac_2_1_clk_converter_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -295,7 +292,7 @@ proc create_root_design { parentCell } {
|
||||
set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.Clock_Frequency {368.64} \
|
||||
CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \
|
||||
CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7}\
|
||||
CONFIG.Coefficient_Fractional_Bits {0} \
|
||||
CONFIG.Coefficient_Sets {1} \
|
||||
CONFIG.Coefficient_Sign {Signed} \
|
||||
@@ -333,10 +330,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name duc_saturate
|
||||
set block_cell_name duc_saturate
|
||||
if { [catch {set duc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $duc_saturate eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -83,10 +83,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -107,19 +107,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -134,7 +134,7 @@ xilinx.com:ip:fir_compiler:7.2\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -144,7 +144,7 @@ xilinx.com:ip:fir_compiler:7.2\
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
@@ -162,7 +162,7 @@ duc_400m_saturate\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
@@ -171,14 +171,14 @@ duc_400m_saturate\
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -202,14 +202,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -232,28 +232,21 @@ proc create_root_design { parentCell } {
|
||||
set dac_data_out_tdata [ create_bd_port -dir O -from 255 -to 0 -type data dac_data_out_tdata ]
|
||||
set dac_data_out_tready [ create_bd_port -dir I -type data dac_data_out_tready ]
|
||||
set dac_data_out_tvalid [ create_bd_port -dir O -type data dac_data_out_tvalid ]
|
||||
set data_clk [ create_bd_port -dir I -type clk data_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {122880000} \
|
||||
] $data_clk
|
||||
set data_clk_2x [ create_bd_port -dir I -type clk data_clk_2x ]
|
||||
set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ]
|
||||
set data_clk_2x [ create_bd_port -dir I -type clk -freq_hz 245760000 data_clk_2x ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk2x} \
|
||||
CONFIG.FREQ_HZ {245760000} \
|
||||
] $data_clk_2x
|
||||
set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {184320000} \
|
||||
] $rfdc_clk
|
||||
set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ]
|
||||
|
||||
# Create instance: dac_gearbox_4x2_0, and set properties
|
||||
set block_name dac_gearbox_4x2
|
||||
set block_cell_name dac_gearbox_4x2_0
|
||||
if { [catch {set dac_gearbox_4x2_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $dac_gearbox_4x2_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -261,10 +254,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name dac_gearbox_6x8
|
||||
set block_cell_name dac_gearbox_6x8_0
|
||||
if { [catch {set dac_gearbox_6x8_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $dac_gearbox_6x8_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -272,13 +265,13 @@ proc create_root_design { parentCell } {
|
||||
set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.Clock_Frequency {245.76} \
|
||||
CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \
|
||||
CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7}\
|
||||
CONFIG.Coefficient_Fractional_Bits {0} \
|
||||
CONFIG.Coefficient_Sets {1} \
|
||||
CONFIG.Coefficient_Sign {Signed} \
|
||||
CONFIG.Coefficient_Structure {Inferred} \
|
||||
CONFIG.Coefficient_Width {18} \
|
||||
CONFIG.ColumnConfig {27} \
|
||||
CONFIG.ColumnConfig {14} \
|
||||
CONFIG.Decimation_Rate {1} \
|
||||
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
|
||||
CONFIG.Filter_Type {Interpolation} \
|
||||
@@ -300,10 +293,10 @@ proc create_root_design { parentCell } {
|
||||
set block_name duc_400m_saturate
|
||||
set block_cell_name duc_400m_saturate_0
|
||||
if { [catch {set duc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $duc_400m_saturate_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
|
||||
@@ -12,18 +12,22 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ADDN_UI_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.BURST_LENGTH">8</spirit:configurableElementValue>
|
||||
@@ -41,6 +45,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
@@ -65,7 +70,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -95,7 +100,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI_CTRL.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -109,8 +114,9 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C0_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SYSTEM_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_ADDR_WIDTH">29</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.APP_DATA_WIDTH">512</spirit:configurableElementValue>
|
||||
@@ -155,6 +161,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DM_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQS_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_DQ_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_HR_MIN_FREQ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IO_VOLTAGE">1.2V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_IS_CUSTOM">false</spirit:configurableElementValue>
|
||||
@@ -174,6 +181,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MODEL_SPEED_GRADE">DDR4_750_Timing</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_MR2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_Mem_Add_Map">ROW_COLUMN_BANK</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_ODT_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_OUTPUT_DRV">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0.DDR4_RANK_WIDTH">1</spirit:configurableElementValue>
|
||||
@@ -244,6 +252,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.M_ADDN_UI_CLKOUT4_PHASE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.Simulation_Mode">BFM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.System_Clock">Differential</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT1_FREQ_HZ">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT2_FREQ_HZ">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDN_UI_CLKOUT3_FREQ_HZ">None</spirit:configurableElementValue>
|
||||
@@ -311,6 +320,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataMask">DM_NO_DBI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_DataWidth">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_EN_PARITY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Ecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_Enable_LVAUX">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C0.DDR4_InputClockPeriod">10000</spirit:configurableElementValue>
|
||||
@@ -360,12 +370,14 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_TERM_SYSCLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Debug_Signal">Disable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Default_Bank_Selections">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_PP_4R_MIR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_SysPorts">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Example_TG">SIMPLE_TG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IOPowerReduction">OFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IO_Power_Reduction">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IS_FROM_PHY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_DBG_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MCS_WO_DSP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_Controller">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PARTIAL_RECONFIG_FLOW_MIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PING_PONG_PHY">1</spirit:configurableElementValue>
|
||||
@@ -393,19 +405,17 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">73068</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1_AR73068</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.C0_DDR4_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
@@ -443,6 +453,38 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_MemoryPart" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C0.DDR4_TimePeriod" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"c0_ddr4_act_n":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_adr":[{"direction":"out","physical_left":"16","physical_right":"0","is_vector":"true"}],"c0_ddr4_aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_ba":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"c0_ddr4_bg":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_ck_c":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_ck_t":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_cke":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_cs_n":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_dm_dbi_n":[{"direction":"inout","physical_left":"7","physical_right":"0","is_vector":"true"}
|
||||
],"c0_ddr4_dq":[{"direction":"inout","physical_left":"63","physical_right":"0","is_vector":"true"}],"c0_ddr4_dqs_c":[{"direction":"inout","physical_left":"7","physical_right":"0","is_vector":"true"}],"c0_ddr4_dqs_t":[{"direction":"inout","physical_left":"7","physical_right":"0","is_vector":"true"}],"c0_ddr4_odt":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_reset_n":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_araddr":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arburst":[{"direction":"in","physical_left":"1","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arcache":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arid":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arlen":[{"direction":"in","physical_left":"7","physical_right":"0","is
|
||||
_vector":"true"}],"c0_ddr4_s_axi_arlock":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arprot":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arqos":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_arsize":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_arvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_awaddr":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awburst":[{"direction":"in","physical_left":"1","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awcache":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awid":[{"direction":"in
|
||||
","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awlen":[{"direction":"in","physical_left":"7","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awlock":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awprot":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awqos":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_awsize":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_awvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_bid":[{"direction":"out","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_bready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"
|
||||
}],"c0_ddr4_s_axi_bresp":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_bvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_rdata":[{"direction":"out","physical_left":"511","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_rid":[{"direction":"out","physical_left":"3","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_rlast":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_rready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_rresp":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_rvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_wdata":[{"direction":"in","physical_left":"511","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_wlast":[{"direction":"in","physical_le
|
||||
ft":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_wready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_s_axi_wstrb":[{"direction":"in","physical_left":"63","physical_right":"0","is_vector":"true"}],"c0_ddr4_s_axi_wvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_ui_clk":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_ddr4_ui_clk_sync_rst":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_init_calib_complete":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_sys_clk_n":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"c0_sys_clk_p":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"dbg_bus":[{"direction":"out","physical_left":"511","physical_right":"0","is_vector":"true"}],"dbg_clk":[{"direction":"out
|
||||
","physical_left":"0","physical_right":"0","is_vector":"false"}],"sys_rst":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"C0_DDR4":{"vlnv":"xilinx.com:interface:ddr4:1.0","abstraction_type":"xilinx.com:interface:ddr4_rtl:1.0","mode":"master","parameters":{"AXI_ARBITRATION_SCHEME":[{"value":"TDM","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"BOARD.ASSOCIATED_PARAM":[{"value":"C0_DDR4_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"BURST_LENGTH":[{"value":"8","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CAN_DEBUG":[{"value":"false","value_src":"default","value_permission":"user","resolve_ty
|
||||
pe":"generated","format":"bool","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CAS_LATENCY":[{"value":"11","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CAS_WRITE_LATENCY":[{"value":"11","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CS_ENABLED":[{"value":"true","value_src":"default","value_permission":"user","resolve_type":"generated","format":"bool","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CUSTOM_PARTS":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"DATA_MASK_ENABLED":[{"value":"true","value_src":"default","value_permission":"user","resolve_type":"generated","format":"bool","usage":"none","is_ips_inf
|
||||
erred":true,"is_static_object":false}],"DATA_WIDTH":[{"value":"8","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"MEMORY_PART":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"MEMORY_TYPE":[{"value":"COMPONENTS","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"MEM_ADDR_MAP":[{"value":"ROW_COLUMN_BANK","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SLOT":[{"value":"Single","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TIMEPERIOD_
|
||||
PS":[{"value":"1250","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"ACT_N":[{"physical_name":"c0_ddr4_act_n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ADR":[{"physical_name":"c0_ddr4_adr","physical_left":"16","physical_right":"0","logical_left":"16","logical_right":"0","port_maps_used":"none"}],"BA":[{"physical_name":"c0_ddr4_ba","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"BG":[{"physical_name":"c0_ddr4_bg","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"CKE":[{"physical_name":"c0_ddr4_cke","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"CK_C":[{"physical_name":"c0_ddr4_ck_c","physical_left":"0","physical_right":"0","lo
|
||||
gical_left":"0","logical_right":"0","port_maps_used":"none"}],"CK_T":[{"physical_name":"c0_ddr4_ck_t","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"CS_N":[{"physical_name":"c0_ddr4_cs_n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"C_ID":[{"physical_name":"c0_ddr4_c","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"DM_N":[{"physical_name":"c0_ddr4_dm_dbi_n","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"DQ":[{"physical_name":"c0_ddr4_dq","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}],"DQS_C":[{"physical_name":"c0_ddr4_dqs_c","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"DQS_T":[{"physical_name":"c0_ddr4_dqs_t","physical_left":"7
|
||||
","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"ODT":[{"physical_name":"c0_ddr4_odt","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"PAR":[{"physical_name":"c0_ddr4_parity","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RESET_N":[{"physical_name":"c0_ddr4_reset_n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"C0_DDR4_ARESETN":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all
|
||||
","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"c0_ddr4_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"C0_DDR4_CLOCK":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"C0_DDR4_S_AXI:C0_DDR4_S_AXI_CTRL","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"c0_ddr4_aresetn:c0_ddr4_ui_clk_sync_rst","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[
|
||||
{"value":"2.5e+08","value_src":"default","value_permission":"user","resolve_type":"dependent","format":"float","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.00","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"float","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"CLK":[{"physical_name":"c0_ddr4_ui_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"C0_DDR4_RESET":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl
|
||||
:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"c0_ddr4_ui_clk_sync_rst","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"C0_DDR4_S_AXI":{"vlnv":"xilinx.com:interface:aximm:1.0","abstraction_type":"xilinx.com:interface:aximm_rtl:1.0","mode":"slave","memory_map_ref":"C0_DDR4_MEMORY_MAP","parameters":{"ADDR_WIDTH":[{"value":"32","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"ARUSER_WIDTH":[{"value":"0","value_
|
||||
src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"AWUSER_WIDTH":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"BUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"DATA_WIDTH":[{"value":"512","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"2.5e+08","value_src":"default","value_permi
|
||||
ssion":"user","resolve_type":"dependent","format":"float","usage":"all","is_ips_inferred":false,"is_static_object":true}],"HAS_BRESP":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_BURST":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_CACHE":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_LOCK":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_PROT":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"
|
||||
long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_QOS":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_REGION":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_RRESP":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"HAS_WSTRB":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"ID_WIDTH":[{"value":"4","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_infe
|
||||
rred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"MAX_BURST_LENGTH":[{"value":"256","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_OUTSTANDING":[{"value":"2","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_THREADS":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_OUTSTANDING":[{"value":"2","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred
|
||||
":true,"is_static_object":false}],"NUM_WRITE_THREADS":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"PROTOCOL":[{"value":"AXI4","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"READ_WRITE_MODE":[{"value":"READ_WRITE","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"RUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred"
|
||||
:true,"is_static_object":false}],"RUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"SUPPORTS_NARROW_BURST":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"WUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}],"WUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"simulation.tlm","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"ARADDR":[{"physical_name":"c0_ddr4_s_axi_araddr","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}
|
||||
],"ARBURST":[{"physical_name":"c0_ddr4_s_axi_arburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"ARCACHE":[{"physical_name":"c0_ddr4_s_axi_arcache","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARID":[{"physical_name":"c0_ddr4_s_axi_arid","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARLEN":[{"physical_name":"c0_ddr4_s_axi_arlen","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"ARLOCK":[{"physical_name":"c0_ddr4_s_axi_arlock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARPROT":[{"physical_name":"c0_ddr4_s_axi_arprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"ARQOS":[{"physical_name":"c0_ddr4_s_axi_arqos","physical_left"
|
||||
:"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARREADY":[{"physical_name":"c0_ddr4_s_axi_arready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARSIZE":[{"physical_name":"c0_ddr4_s_axi_arsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"ARUSER":[{"physical_name":"c0_ddr4_s_axi_aruser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARVALID":[{"physical_name":"c0_ddr4_s_axi_arvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWADDR":[{"physical_name":"c0_ddr4_s_axi_awaddr","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"AWBURST":[{"physical_name":"c0_ddr4_s_axi_awburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_r
|
||||
ight":"0","port_maps_used":"none"}],"AWCACHE":[{"physical_name":"c0_ddr4_s_axi_awcache","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"AWID":[{"physical_name":"c0_ddr4_s_axi_awid","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"AWLEN":[{"physical_name":"c0_ddr4_s_axi_awlen","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"AWLOCK":[{"physical_name":"c0_ddr4_s_axi_awlock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWPROT":[{"physical_name":"c0_ddr4_s_axi_awprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWQOS":[{"physical_name":"c0_ddr4_s_axi_awqos","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"AWREADY":[{"physical_name":"c0_d
|
||||
dr4_s_axi_awready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWSIZE":[{"physical_name":"c0_ddr4_s_axi_awsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWUSER":[{"physical_name":"c0_ddr4_s_axi_awuser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWVALID":[{"physical_name":"c0_ddr4_s_axi_awvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BID":[{"physical_name":"c0_ddr4_s_axi_bid","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"BREADY":[{"physical_name":"c0_ddr4_s_axi_bready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BRESP":[{"physical_name":"c0_ddr4_s_axi_bresp","physical_left":"1","physical_right":"0","logical_
|
||||
left":"1","logical_right":"0","port_maps_used":"none"}],"BVALID":[{"physical_name":"c0_ddr4_s_axi_bvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RDATA":[{"physical_name":"c0_ddr4_s_axi_rdata","physical_left":"511","physical_right":"0","logical_left":"511","logical_right":"0","port_maps_used":"none"}],"RID":[{"physical_name":"c0_ddr4_s_axi_rid","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"RLAST":[{"physical_name":"c0_ddr4_s_axi_rlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RREADY":[{"physical_name":"c0_ddr4_s_axi_rready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RRESP":[{"physical_name":"c0_ddr4_s_axi_rresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"RVALID":[{"phy
|
||||
sical_name":"c0_ddr4_s_axi_rvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WDATA":[{"physical_name":"c0_ddr4_s_axi_wdata","physical_left":"511","physical_right":"0","logical_left":"511","logical_right":"0","port_maps_used":"none"}],"WLAST":[{"physical_name":"c0_ddr4_s_axi_wlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WREADY":[{"physical_name":"c0_ddr4_s_axi_wready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WSTRB":[{"physical_name":"c0_ddr4_s_axi_wstrb","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}],"WVALID":[{"physical_name":"c0_ddr4_s_axi_wvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"C0_SYS_CLK":{"vlnv":"xilinx.com:interface:diff_clock:1.0","abstraction_type
|
||||
":"xilinx.com:interface:diff_clock_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"C0_CLOCK_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CAN_DEBUG":[{"value":"false","value_src":"default","value_permission":"user","resolve_type":"generated","format":"bool","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK_N":[{"physical_name":"c0_sys_clk_n","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"CLK_P":[{"physical_name":"c0_sys_clk_p","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"SYSTEM_RESET":{"vlnv"
|
||||
:"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"RESET_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"sys_rst","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}},"memory_maps":{"C0_DDR4_MEMORY_MAP":{"address_blocks":{"C0_DDR4_ADDRESS_BLOCK":[{"base_address":"0","range":"4294967296","display_n
|
||||
ame":"","description":"","usage":"memory","access":"read-write"}]}},"C0_DDR4_MEMORY_MAP_CTRL":{"address_blocks":{"C0_REG":[{"base_address":"0","range":"4096","display_name":"","description":"","usage":"register","access":"read-write"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@@ -21,7 +21,7 @@ sim/eth_100g_bd.v\
|
||||
ip/*/ip_0/sim/*.v\
|
||||
ip/*/sim/*.h\
|
||||
ip/*/sim/*.v\
|
||||
ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v2_6_1/*.v\
|
||||
ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v3_1_4/*.v\
|
||||
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/*.v\
|
||||
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/header_files/*.h\
|
||||
ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0.v\
|
||||
|
||||
@@ -80,6 +80,7 @@ module eth_100g #(
|
||||
end
|
||||
end
|
||||
|
||||
// synthesis translate_off
|
||||
//extra simulation checks
|
||||
localparam USE_MAC_CHECKS = 1;
|
||||
if (USE_MAC_CHECKS) begin
|
||||
@@ -124,6 +125,7 @@ module eth_100g #(
|
||||
assert (mgt_rx.TLAST == 1) else
|
||||
$fatal(1, "mgt_rx.TLAST must be enabled");
|
||||
end
|
||||
// synthesis translate_on
|
||||
|
||||
AxiStreamIf #(.DATA_WIDTH(512),.TUSER(0),.TKEEP(0))
|
||||
eth100g_tx(mgt_clk,mgt_rst);
|
||||
@@ -1130,23 +1132,11 @@ module eth_100g #(
|
||||
eth_100g_bd eth_100g_bd_i (
|
||||
.refclk_clk_n(refclk_n),
|
||||
.refclk_clk_p(refclk_p),
|
||||
.gt_rx_gt_port_0_n(rx_n[0]),
|
||||
.gt_rx_gt_port_0_p(rx_p[0]),
|
||||
.gt_rx_gt_port_1_n(rx_n[1]),
|
||||
.gt_rx_gt_port_1_p(rx_p[1]),
|
||||
.gt_rx_gt_port_2_n(rx_n[2]),
|
||||
.gt_rx_gt_port_2_p(rx_p[2]),
|
||||
.gt_rx_gt_port_3_n(rx_n[3]),
|
||||
.gt_rx_gt_port_3_p(rx_p[3]),
|
||||
.gt_serial_port_0_grx_n(rx_n),
|
||||
.gt_serial_port_0_grx_p(rx_p),
|
||||
.gt_serial_port_0_gtx_n(tx_n),
|
||||
.gt_serial_port_0_gtx_p(tx_p),
|
||||
.init_clk(clk100),
|
||||
.gt_tx_gt_port_0_n(tx_n[0]),
|
||||
.gt_tx_gt_port_0_p(tx_p[0]),
|
||||
.gt_tx_gt_port_1_n(tx_n[1]),
|
||||
.gt_tx_gt_port_1_p(tx_p[1]),
|
||||
.gt_tx_gt_port_2_n(tx_n[2]),
|
||||
.gt_tx_gt_port_2_p(tx_p[2]),
|
||||
.gt_tx_gt_port_3_n(tx_n[3]),
|
||||
.gt_tx_gt_port_3_p(tx_p[3]),
|
||||
.sys_reset(areset),
|
||||
.usr_rx_reset(usr_rx_reset),
|
||||
.usr_tx_reset(usr_tx_reset),
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -76,10 +76,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -100,19 +100,19 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -123,12 +123,12 @@ set bCheckIPsPassed 1
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:cmac_usplus:2.6\
|
||||
xilinx.com:ip:cmac_usplus:3.1\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -138,14 +138,14 @@ xilinx.com:ip:xlconstant:1.1\
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -169,14 +169,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -194,9 +194,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set eth100g_tx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_tx ]
|
||||
|
||||
set gt_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_rx ]
|
||||
|
||||
set gt_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_tx ]
|
||||
set gt_serial_port_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_serial_port_0 ]
|
||||
|
||||
set refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 refclk ]
|
||||
set_property -dict [ list \
|
||||
@@ -246,10 +244,7 @@ proc create_root_design { parentCell } {
|
||||
] $gt_txusrclk2
|
||||
set init_clk [ create_bd_port -dir I -type clk init_clk ]
|
||||
set pm_tick [ create_bd_port -dir I pm_tick ]
|
||||
set rx_clk [ create_bd_port -dir I -type clk rx_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {322265625} \
|
||||
] $rx_clk
|
||||
set rx_clk [ create_bd_port -dir I -type clk -freq_hz 322265625 rx_clk ]
|
||||
set s_axi_aclk [ create_bd_port -dir I -type clk s_axi_aclk ]
|
||||
set s_axi_sreset [ create_bd_port -dir I -type rst s_axi_sreset ]
|
||||
set_property -dict [ list \
|
||||
@@ -267,7 +262,7 @@ proc create_root_design { parentCell } {
|
||||
set usr_tx_reset [ create_bd_port -dir O -type rst usr_tx_reset ]
|
||||
|
||||
# Create instance: cmac_usplus_0, and set properties
|
||||
set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:2.6 cmac_usplus_0 ]
|
||||
set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.CMAC_CAUI4_MODE {1} \
|
||||
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \
|
||||
@@ -289,7 +284,7 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.LANE7_GT_LOC {NA} \
|
||||
CONFIG.LANE8_GT_LOC {NA} \
|
||||
CONFIG.LANE9_GT_LOC {NA} \
|
||||
CONFIG.NUM_LANES {4} \
|
||||
CONFIG.NUM_LANES {4x25} \
|
||||
CONFIG.RX_CHECK_ACK {0} \
|
||||
CONFIG.RX_EQ_MODE {AUTO} \
|
||||
CONFIG.RX_FLOW_CONTROL {1} \
|
||||
@@ -312,8 +307,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net RefClk_1 [get_bd_intf_ports refclk] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk]
|
||||
connect_bd_intf_net -intf_net Rx_1 [get_bd_intf_ports gt_rx] [get_bd_intf_pins cmac_usplus_0/gt_rx]
|
||||
connect_bd_intf_net -intf_net cmac_usplus_0_gt_tx [get_bd_intf_ports gt_tx] [get_bd_intf_pins cmac_usplus_0/gt_tx]
|
||||
connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_ports gt_serial_port_0] [get_bd_intf_pins cmac_usplus_0/gt_serial_port]
|
||||
connect_bd_intf_net -intf_net cmac_usplus_0_lbus_rx [get_bd_intf_ports eth100g_rx] [get_bd_intf_pins cmac_usplus_0/lbus_rx]
|
||||
connect_bd_intf_net -intf_net eth_100g_tx_1 [get_bd_intf_ports eth100g_tx] [get_bd_intf_pins cmac_usplus_0/lbus_tx]
|
||||
connect_bd_intf_net -intf_net sDrp_1 [get_bd_intf_ports core_drp] [get_bd_intf_pins cmac_usplus_0/core_drp]
|
||||
@@ -340,7 +334,7 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net tie_zero_dout [get_bd_pins cmac_usplus_0/gtwiz_reset_rx_datapath] [get_bd_pins cmac_usplus_0/gtwiz_reset_tx_datapath] [get_bd_pins tie_zero/dout]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] SEG_cmac_usplus_0_Reg
|
||||
assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] -force
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -35,7 +35,7 @@ $(AXI4S_SV_SRCS) \
|
||||
#-------------------------------------------------
|
||||
# Testbench Specific
|
||||
#-------------------------------------------------
|
||||
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
|
||||
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5
|
||||
MODELSIM_ARGS += glbl -t 1fs
|
||||
# Define toplevel module
|
||||
TB_TOP_MODULE ?= lbus_all_tb
|
||||
@@ -50,8 +50,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \
|
||||
# Suppressing the following worthless reminder.
|
||||
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
|
||||
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
|
||||
SVLOG_ARGS = -suppress 2583 -keep_delta
|
||||
VLOG_ARGS = -keep_delta
|
||||
SVLOG_ARGS = -suppress 2583 -keep_delta
|
||||
VLOG_ARGS = -keep_delta
|
||||
|
||||
#-------------------------------------------------
|
||||
# Bottom-of-Makefile
|
||||
|
||||
@@ -13,13 +13,15 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -43,7 +45,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -59,7 +61,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -68,12 +70,14 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -98,7 +102,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -114,7 +118,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -123,8 +127,9 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
@@ -509,12 +514,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@@ -569,6 +574,14 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"din":[{"direction":"in","physical_left":"71","physical_right":"0","is_vector":"true"}],"dout":[{"direction":"out","physical_left":"71","physical_right":"0","is_vector":"true"}],"empty":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"full":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_data_count":[{"direction":"out","physical_left":"9","physical_right":"0","is_vector":"true"}],"rd_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rst":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_data_count":[{"direction":"out","physical_left":"9","physical_right":"0","is_vector":"true"}],"wr_en":[{"direction":"in","physical_left":"0","physical_ri
|
||||
ght":"0","is_vector":"false"}]},"interfaces":{"FIFO_READ":{"vlnv":"xilinx.com:interface:fifo_read:1.0","abstraction_type":"xilinx.com:interface:fifo_read_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_EMPTY":[{"physical_name":"almost_empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"EMPTY":[{"physical_name":"empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RD_DATA":[{"physical_name":"dout","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"RD_EN":[{"physical_name":"rd_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"FIFO_WRITE":{"vlnv":"xilinx.com:interface:fifo_write:1.0","abstraction_type":"xilinx.com:interface:fifo_write_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_FULL":[{"physical_name":"almost_full","ph
|
||||
ysical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"FULL":[{"physical_name":"full","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WR_DATA":[{"physical_name":"din","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"WR_EN":[{"physical_name":"wr_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"read_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_infer
|
||||
red":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name"
|
||||
:"rd_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"write_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FR
|
||||
EQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"wr_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@@ -13,13 +13,15 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -43,7 +45,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -59,7 +61,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -68,12 +70,14 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -98,7 +102,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -114,7 +118,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -123,8 +127,9 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
@@ -509,12 +514,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@@ -571,6 +576,14 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.synchronization_stages" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"din":[{"direction":"in","physical_left":"71","physical_right":"0","is_vector":"true"}],"dout":[{"direction":"out","physical_left":"71","physical_right":"0","is_vector":"true"}],"empty":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"full":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rd_data_count":[{"direction":"out","physical_left":"5","physical_right":"0","is_vector":"true"}],"rd_en":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rst":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_clk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"wr_data_count":[{"direction":"out","physical_left":"5","physical_right":"0","is_vector":"true"}],"wr_en":[{"direction":"in","physical_left":"0","physical_ri
|
||||
ght":"0","is_vector":"false"}]},"interfaces":{"FIFO_READ":{"vlnv":"xilinx.com:interface:fifo_read:1.0","abstraction_type":"xilinx.com:interface:fifo_read_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_EMPTY":[{"physical_name":"almost_empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"EMPTY":[{"physical_name":"empty","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RD_DATA":[{"physical_name":"dout","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"RD_EN":[{"physical_name":"rd_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"FIFO_WRITE":{"vlnv":"xilinx.com:interface:fifo_write:1.0","abstraction_type":"xilinx.com:interface:fifo_write_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"ALMOST_FULL":[{"physical_name":"almost_full","ph
|
||||
ysical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"FULL":[{"physical_name":"full","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WR_DATA":[{"physical_name":"din","physical_left":"71","physical_right":"0","logical_left":"71","logical_right":"0","port_maps_used":"none"}],"WR_EN":[{"physical_name":"wr_en","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"read_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_infer
|
||||
red":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name"
|
||||
:"rd_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"write_clk":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FR
|
||||
EQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"wr_clk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@@ -9,11 +9,11 @@
|
||||
<spirit:instanceName>hb47_1to2</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
|
||||
@@ -30,7 +30,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -43,7 +43,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -56,7 +56,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -151,6 +151,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientSource">Vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientVector">-62, 0, 194, 0, -440, 0, 855, 0, -1505, 0, 2478, 0, -3900, 0, 5990, 0, -9187, 0, 14632, 0, -26536, 0, 83009, 131071, 83009, 0, -26536, 0, 14632, 0, -9187, 0, 5990, 0, -3900, 0, 2478, 0, -1505, 0, 855, 0, -440, 0, 194, 0, -62</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Buffer_Type">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_File">no_coe_file_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Reload">false</spirit:configurableElementValue>
|
||||
@@ -160,13 +161,20 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Width">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ColumnConfig">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">hb47_1to2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_Broadcast_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_Column_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_LUT_Pipeline">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_Path_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Not_Required</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_TUSER_Width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Buffer_Type">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Fractional_Bits">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Path_Broadcast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Path_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Sign">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Decimation_Rate">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Half_Band_Centre_Tap">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DisplayReloadOrder">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Architecture">Systolic_Multiply_Accumulate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Selection">1</spirit:configurableElementValue>
|
||||
@@ -184,18 +192,23 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TREADY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multi_Column_Support">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_BRAM_Read_First_Mode">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_SRL_Attributes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Num_Reload_Slots">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Channels">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Paths">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimal_Column_Lengths">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_List">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Selection">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Other">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Buffer_Type">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Rounding_Mode">Convergent_Rounding_to_Even</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Max">0.5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Min">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pattern_List">P4-0,P4-1,P4-2,P4-3,P4-4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pre_Adder_Pipeline">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Preference_For_Other_Storage">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Quantization">Integer_Coefficients</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RateSpecification">Output_Sample_Period</spirit:configurableElementValue>
|
||||
@@ -226,12 +239,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1_AR73068</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@@ -291,6 +304,24 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Sample_Frequency" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Zero_Pack_Factor" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axis_data_tdata":[{"direction":"out","physical_left":"95","physical_right":"0","is_vector":"true"}],"m_axis_data_tuser":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"m_axis_data_tvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axis_data_tdata":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"s_axis_data_tready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axis_data_tvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"M_AXIS_DATA":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"master","parameters":{"CLK_DOMAIN":[{"value
|
||||
":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TKEEP":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TLAST":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TREADY":[{"value":"0","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TSTRB":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","
|
||||
format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"LAYERED_METADATA":[{"value":"undef","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDATA_NUM_BYTES":[{"value":"12","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDEST_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_
|
||||
object":false}],"TID_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TUSER_WIDTH":[{"value":"1","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"TDATA":[{"physical_name":"m_axis_data_tdata","physical_left":"95","physical_right":"0","logical_left":"95","logical_right":"0","port_maps_used":"none"}],"TLAST":[{"physical_name":"m_axis_data_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TREADY":[{"physical_name":"m_axis_data_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TUSER":[{"physical_name":"m_axis_data_tuser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"n
|
||||
one"}],"TVALID":[{"physical_name":"m_axis_data_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"S_AXIS_DATA":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"slave","parameters":{"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TKEEP":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TLAST":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inf
|
||||
erred":true,"is_static_object":false}],"HAS_TREADY":[{"value":"1","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TSTRB":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"LAYERED_METADATA":[{"value":"undef","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDATA_NUM_BYTES":[{"value":"
|
||||
4","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDEST_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TID_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TUSER_WIDTH":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"TDATA":[{"physical_name":"s_axis_data_tdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"TLAST":[{"physical_name":"s_axis_data_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"
|
||||
0","port_maps_used":"none"}],"TREADY":[{"physical_name":"s_axis_data_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TUSER":[{"physical_name":"s_axis_data_tuser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TVALID":[{"physical_name":"s_axis_data_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"aclk_intf":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_CLKEN":[{"value":"aclken","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","us
|
||||
age":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"aresetn","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false
|
||||
}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"aclken_intf":{"vlnv":"xilinx.com:signal:clockenable:1.0","abstraction_type":"xilinx.com:signal:clockenable_rtl:1.0","mode":"slave","parameters":{"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"CE":[{"physical_name":"aclken","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"aresetn_intf":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_
|
||||
src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_config_tlast_missing_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_
|
||||
ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_config_tlast_missing","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_config_tlast_unexpected_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_config_tlast_unexpected","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_data_chanid_incorrect_intf":{
|
||||
"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_data_chanid_incorrect","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_data_tlast_missing_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferr
|
||||
ed":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_data_tlast_missing","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_data_tlast_unexpected_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name
|
||||
":"event_s_data_tlast_unexpected","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_reload_tlast_missing_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_reload_tlast_missing","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_reload_tlast_unexpected_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rt
|
||||
l:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_reload_tlast_unexpected","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@@ -9,11 +9,11 @@
|
||||
<spirit:instanceName>hb47_2to1</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fir_compiler" spirit:version="7.2"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLKEN_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_MISSING_INTF.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EVENT_S_CONFIG_TLAST_UNEXPECTED_INTF.PortWidth">1</spirit:configurableElementValue>
|
||||
@@ -30,7 +30,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDATA_NUM_BYTES">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -43,7 +43,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CONFIG.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -56,7 +56,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DATA.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -69,7 +69,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_RELOAD.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -78,7 +78,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ACCUM_PATH_WIDTHS">35,35,35,35</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL_PATTERN">fixed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE">hb47_2to1.mif</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE_LINES">47</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_FILE_LINES">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEMTYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_MEM_PACKING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_SIGN">0,0,0,0</spirit:configurableElementValue>
|
||||
@@ -86,7 +86,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_PATH_WIDTHS">18,18,18,18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_RELOAD">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COEF_WIDTH">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_CONFIG">47</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_CONFIG">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_MODE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COL_PIPE_LEN">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMPONENT_NAME">hb47_2to1</spirit:configurableElementValue>
|
||||
@@ -115,15 +115,15 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_RATE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERP_RATE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IPBUFF_MEMTYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">52</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_ARRANGEMENT">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_ARRANGEMENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TREADY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_HAS_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TDATA_WIDTH">48</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_DATA_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_CHANNELS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_FILTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MADDS">47</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_MADDS">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_RELOAD_SLOTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_TAPS">47</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPBUFF_MEMTYPE">0</spirit:configurableElementValue>
|
||||
@@ -137,7 +137,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PX_PATH_SRC">2,3,2,3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RELOAD_TDATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ROUND_MODE">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYMMETRY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYMMETRY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_HAS_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_DATA_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
@@ -151,22 +151,30 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientSource">Vector</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CoefficientVector">-62 0 194 0 -440 0 855 0 -1505 0 2478 0 -3900 0 5990 0 -9187 0 14632 0 -26536 0 83009 131071 83009 0 -26536 0 14632 0 -9187 0 5990 0 -3900 0 2478 0 -1505 0 855 0 -440 0 194 0 -62</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Buffer_Type">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_File">hb47.coe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_File">no_coe_file_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Fractional_Bits">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Reload">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sets">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Sign">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Structure">Inferred</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coefficient_Width">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ColumnConfig">47</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ColumnConfig">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">hb47_2to1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_Broadcast_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_Column_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_LUT_Pipeline">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Control_Path_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_Has_TLAST">Not_Required</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_TUSER_Width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Buffer_Type">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Fractional_Bits">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Path_Broadcast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Path_Fanout">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Sign">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Decimation_Rate">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Half_Band_Centre_Tap">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DisplayReloadOrder">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Architecture">Systolic_Multiply_Accumulate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Filter_Selection">1</spirit:configurableElementValue>
|
||||
@@ -184,18 +192,23 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TREADY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.M_DATA_Has_TUSER">Not_Required</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multi_Column_Support">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_BRAM_Read_First_Mode">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.No_SRL_Attributes">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Num_Reload_Slots">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Channels">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Number_Paths">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimal_Column_Lengths">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Goal">Area</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_List">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Optimization_Selection">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Other">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Buffer_Type">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Rounding_Mode">Convergent_Rounding_to_Even</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Max">0.4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Passband_Min">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pattern_List">P4-0,P4-1,P4-2,P4-3,P4-4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pre_Adder_Pipeline">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Preference_For_Other_Storage">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Quantization">Integer_Coefficients</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RateSpecification">Input_Sample_Period</spirit:configurableElementValue>
|
||||
@@ -226,12 +239,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1_AR73068</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@@ -306,6 +319,24 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Stopband_Min" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Zero_Pack_Factor" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"m_axis_data_tdata":[{"direction":"out","physical_left":"47","physical_right":"0","is_vector":"true"}],"m_axis_data_tuser":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"true"}],"m_axis_data_tvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axis_data_tdata":[{"direction":"in","physical_left":"63","physical_right":"0","is_vector":"true"}],"s_axis_data_tready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axis_data_tvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"M_AXIS_DATA":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"master","parameters":{"CLK_DOMAIN":[{"value
|
||||
":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TKEEP":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TLAST":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TREADY":[{"value":"0","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TSTRB":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","
|
||||
format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"LAYERED_METADATA":[{"value":"undef","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDATA_NUM_BYTES":[{"value":"6","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDEST_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_o
|
||||
bject":false}],"TID_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TUSER_WIDTH":[{"value":"1","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"TDATA":[{"physical_name":"m_axis_data_tdata","physical_left":"47","physical_right":"0","logical_left":"47","logical_right":"0","port_maps_used":"none"}],"TLAST":[{"physical_name":"m_axis_data_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TREADY":[{"physical_name":"m_axis_data_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TUSER":[{"physical_name":"m_axis_data_tuser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"no
|
||||
ne"}],"TVALID":[{"physical_name":"m_axis_data_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"S_AXIS_DATA":{"vlnv":"xilinx.com:interface:axis:1.0","abstraction_type":"xilinx.com:interface:axis_rtl:1.0","mode":"slave","parameters":{"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TKEEP":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TLAST":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_infe
|
||||
rred":true,"is_static_object":false}],"HAS_TREADY":[{"value":"1","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_TSTRB":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"LAYERED_METADATA":[{"value":"undef","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDATA_NUM_BYTES":[{"value":"8
|
||||
","value_src":"auto","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TDEST_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TID_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"TUSER_WIDTH":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"TDATA":[{"physical_name":"s_axis_data_tdata","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}],"TLAST":[{"physical_name":"s_axis_data_tlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0
|
||||
","port_maps_used":"none"}],"TREADY":[{"physical_name":"s_axis_data_tready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TUSER":[{"physical_name":"s_axis_data_tuser","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"TVALID":[{"physical_name":"s_axis_data_tvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"aclk_intf":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_CLKEN":[{"value":"aclken","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usa
|
||||
ge":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"aresetn","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}
|
||||
],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"aclken_intf":{"vlnv":"xilinx.com:signal:clockenable:1.0","abstraction_type":"xilinx.com:signal:clockenable_rtl:1.0","mode":"slave","parameters":{"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"CE":[{"physical_name":"aclken","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"aresetn_intf":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_s
|
||||
rc":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_config_tlast_missing_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_i
|
||||
ps_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_config_tlast_missing","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_config_tlast_unexpected_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_config_tlast_unexpected","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_data_chanid_incorrect_intf":{"
|
||||
vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_data_chanid_incorrect","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_data_tlast_missing_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferre
|
||||
d":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_data_tlast_missing","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_data_tlast_unexpected_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name"
|
||||
:"event_s_data_tlast_unexpected","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_reload_tlast_missing_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_reload_tlast_missing","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"event_s_reload_tlast_unexpected_intf":{"vlnv":"xilinx.com:signal:interrupt:1.0","abstraction_type":"xilinx.com:signal:interrupt_rtl
|
||||
:1.0","mode":"master","parameters":{"PortWidth":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SENSITIVITY":[{"value":"EDGE_RISING","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"INTERRUPT":[{"physical_name":"event_s_reload_tlast_unexpected","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder]
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2019.1
|
||||
set scripts_vivado_version 2021.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
@@ -83,10 +83,10 @@ if { ${design_name} eq "" } {
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
@@ -107,11 +107,11 @@ if { ${design_name} eq "" } {
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
@@ -123,10 +123,10 @@ if { ${design_name} eq "" } {
|
||||
[15:8] = invert DAC channels
|
||||
[7:0] = invert ADC channels" [get_bd_designs $design_name]
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
@@ -143,16 +143,16 @@ xilinx.com:ip:xlconcat:2.1\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
xilinx.com:ip:clk_wiz:6.0\
|
||||
xilinx.com:ip:axi_gpio:2.0\
|
||||
xilinx.com:ip:usp_rf_data_converter:2.1\
|
||||
xilinx.com:ip:usp_rf_data_converter:2.5\
|
||||
xilinx.com:ip:xlslice:1.0\
|
||||
xilinx.com:ip:axi_protocol_converter:2.1\
|
||||
xilinx.com:ip:axi_dma:7.1\
|
||||
xilinx.com:ip:smartconnect:1.0\
|
||||
xilinx.com:ip:util_ds_buf:2.1\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
@@ -162,7 +162,7 @@ xilinx.com:ip:util_ds_buf:2.1\
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
@@ -182,7 +182,7 @@ gpio_to_axis_mux\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
@@ -191,14 +191,14 @@ gpio_to_axis_mux\
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
@@ -213,21 +213,21 @@ proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -252,13 +252,13 @@ proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
|
||||
create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll
|
||||
|
||||
# Create instance: rfdc_clk_1x_buf, and set properties
|
||||
set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_1x_buf ]
|
||||
set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_1x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rfdc_clk_1x_buf
|
||||
|
||||
# Create instance: rfdc_clk_2x_buf, and set properties
|
||||
set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_2x_buf ]
|
||||
set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_2x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rfdc_clk_2x_buf
|
||||
@@ -281,21 +281,21 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -347,10 +347,10 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } {
|
||||
set block_name gpio_to_axis_mux
|
||||
set block_cell_name gpio_to_axis_mux_0
|
||||
if { [catch {set gpio_to_axis_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $gpio_to_axis_mux_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
set_property -dict [ list \
|
||||
@@ -385,21 +385,21 @@ proc create_hier_cell_ThresholdRegister { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -475,21 +475,21 @@ proc create_hier_cell_eth_dma_internal { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -577,21 +577,21 @@ proc create_hier_cell_axi_interconnect_common { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -666,21 +666,21 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -800,10 +800,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set block_name capture_sysref
|
||||
set block_cell_name capture_sysref
|
||||
if { [catch {set capture_sysref [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $capture_sysref eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -823,10 +823,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set block_name clock_gates
|
||||
set block_cell_name clock_gates_0
|
||||
if { [catch {set clock_gates_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $clock_gates_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -941,7 +941,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers
|
||||
|
||||
# Create instance: rf_data_converter, and set properties
|
||||
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.1 rf_data_converter ]
|
||||
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ADC0_Enable {1} \
|
||||
CONFIG.ADC0_Fabric_Freq {184.320} \
|
||||
@@ -1200,10 +1200,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set block_name rf_nco_reset
|
||||
set block_cell_name rf_nco_reset_0
|
||||
if { [catch {set rf_nco_reset_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $rf_nco_reset_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -1211,10 +1211,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set block_name rf_reset_controller
|
||||
set block_cell_name rf_reset_controller_0
|
||||
if { [catch {set rf_reset_controller_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $rf_reset_controller_0 eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
@@ -1354,21 +1354,21 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ps() - Empty argument(s)!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ps() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -1441,6 +1441,11 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
# Create instance: cpld_jtag_engine, and set properties
|
||||
set cpld_jtag_engine [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 cpld_jtag_engine ]
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \
|
||||
] [get_bd_intf_pins /ps/cpld_jtag_engine/S_AXI]
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \
|
||||
@@ -1951,8 +1956,14 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
CONFIG.PSU_MIO_9_POLARITY {Default} \
|
||||
CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \
|
||||
CONFIG.PSU_MIO_9_SLEW {slow} \
|
||||
CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART 1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \
|
||||
CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \
|
||||
CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI\
|
||||
1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0\
|
||||
MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART\
|
||||
1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1\
|
||||
MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\
|
||||
0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\
|
||||
3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3}\
|
||||
CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
|
||||
CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
|
||||
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
|
||||
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \
|
||||
@@ -2664,6 +2675,7 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
|
||||
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
|
||||
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
|
||||
CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
|
||||
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
|
||||
CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
|
||||
CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
|
||||
@@ -2771,14 +2783,37 @@ proc create_hier_cell_ps { parentCell nameHier } {
|
||||
CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
|
||||
CONFIG.PSU__PROTECTION__DEBUG {0} \
|
||||
CONFIG.PSU__PROTECTION__ENABLE {0} \
|
||||
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
|
||||
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000\
|
||||
;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware}\
|
||||
CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
|
||||
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \
|
||||
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
|
||||
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \
|
||||
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB\
|
||||
;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB\
|
||||
;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000\
|
||||
;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\
|
||||
Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\
|
||||
;WrAllowed:Read/Write;subsystemId:PMU Firmware}\
|
||||
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
|
||||
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
|
||||
CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
|
||||
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
|
||||
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
|
||||
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
|
||||
Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
|
||||
CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \
|
||||
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
|
||||
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
|
||||
@@ -3046,14 +3081,14 @@ proc create_root_design { parentCell } {
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
@@ -3411,18 +3446,16 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.POLARITY {ACTIVE_HIGH} \
|
||||
] $adc_reset_pulse_dclk
|
||||
set adc_rfdc_axi_resetn_rclk [ create_bd_port -dir O adc_rfdc_axi_resetn_rclk ]
|
||||
set bus_clk [ create_bd_port -dir I -type clk bus_clk ]
|
||||
set bus_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 bus_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {m_axis_eth_dma:s_axis_eth_dma:s_axi_hpc1} \
|
||||
CONFIG.ASSOCIATED_RESET {bus_rstn} \
|
||||
CONFIG.FREQ_HZ {200000000} \
|
||||
] $bus_clk
|
||||
set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ]
|
||||
set clk40 [ create_bd_port -dir I -type clk clk40 ]
|
||||
set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {m_axi_app:m_axi_mpm_ep:m_axi_core:m_axi_rpu:m_axi_eth_internal} \
|
||||
CONFIG.ASSOCIATED_RESET {clk40_rstn} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $clk40
|
||||
set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ]
|
||||
set dac_data_in_resetn_dclk [ create_bd_port -dir O dac_data_in_resetn_dclk ]
|
||||
@@ -3473,10 +3506,7 @@ proc create_root_design { parentCell } {
|
||||
set pl_resetn1 [ create_bd_port -dir O -type rst pl_resetn1 ]
|
||||
set pl_resetn2 [ create_bd_port -dir O -type rst pl_resetn2 ]
|
||||
set pl_resetn3 [ create_bd_port -dir O -type rst pl_resetn3 ]
|
||||
set pll_ref_clk_in [ create_bd_port -dir I -type clk pll_ref_clk_in ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {61440000} \
|
||||
] $pll_ref_clk_in
|
||||
set pll_ref_clk_in [ create_bd_port -dir I -type clk -freq_hz 61440000 pll_ref_clk_in ]
|
||||
set pll_ref_clk_out [ create_bd_port -dir O -type clk pll_ref_clk_out ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {61440000} \
|
||||
@@ -3494,16 +3524,14 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.FREQ_HZ {368640000} \
|
||||
] $rfdc_clk_2x
|
||||
set rfdc_irq [ create_bd_port -dir O -type intr rfdc_irq ]
|
||||
set s_axi_hp0_aclk [ create_bd_port -dir I -type clk s_axi_hp0_aclk ]
|
||||
set s_axi_hp0_aclk [ create_bd_port -dir I -type clk -freq_hz 40000000 s_axi_hp0_aclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {s_axi_hp0} \
|
||||
CONFIG.ASSOCIATED_RESET {s_axi_hp0_aresetn} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $s_axi_hp0_aclk
|
||||
set s_axi_hp1_aclk [ create_bd_port -dir I -type clk s_axi_hp1_aclk ]
|
||||
set s_axi_hp1_aclk [ create_bd_port -dir I -type clk -freq_hz 40000000 s_axi_hp1_aclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {s_axi_hp1} \
|
||||
CONFIG.FREQ_HZ {40000000} \
|
||||
] $s_axi_hp1_aclk
|
||||
set s_axi_hpc0_aclk [ create_bd_port -dir I -type clk s_axi_hpc0_aclk ]
|
||||
set_property -dict [ list \
|
||||
@@ -3616,51 +3644,45 @@ proc create_root_design { parentCell } {
|
||||
connect_bd_net -net sysref_pl_in_1 [get_bd_ports sysref_pl_in] [get_bd_pins rfdc/sysref_pl_in]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x0010000A4000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] SEG_axi_eth_dma_internal_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000155000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000154000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] SEG_axi_gpio_data_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] SEG_cpld_jtag_engine_reg0
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x001000140000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] SEG_data_clock_mmcm_Reg
|
||||
create_bd_addr_seg -range 0x000200000000 -offset 0x001200000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] SEG_m_axi_app_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x0010000A0000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_core/Reg] SEG_m_axi_core_0_Reg
|
||||
create_bd_addr_seg -range 0x00004000 -offset 0x0010000A8000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg
|
||||
create_bd_addr_seg -range 0x00020000 -offset 0x001000080000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] SEG_m_axi_mpm_ep_Reg
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x80000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] SEG_m_axi_rpu_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000156000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] SEG_reg_clock_gate_control_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000150000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] SEG_reg_invert_iq_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000151000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] SEG_reg_reset_mmcm_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000153000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] SEG_reg_rf_axi_status_Reg
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x001000152000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] SEG_reg_rf_reset_control_Reg
|
||||
create_bd_addr_seg -range 0x00040000 -offset 0x001000100000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] SEG_rf_data_converter_Reg
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_HIGH] SEG_inst_zynq_ps_HP0_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_LOW] SEG_inst_zynq_ps_HP0_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_LPS_OCM] SEG_inst_zynq_ps_HP0_LPS_OCM
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_HIGH] SEG_inst_zynq_ps_HP1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_LOW] SEG_inst_zynq_ps_HP1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_LPS_OCM] SEG_inst_zynq_ps_HP1_LPS_OCM
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_HIGH] SEG_inst_zynq_ps_HPC0_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_LOW] SEG_inst_zynq_ps_HPC0_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_LPS_OCM] SEG_inst_zynq_ps_HPC0_LPS_OCM
|
||||
create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
assign_bd_address -offset 0x0010000A4000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] -force
|
||||
assign_bd_address -offset 0x001000155000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000154000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] -force
|
||||
assign_bd_address -offset 0x001000140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] -force
|
||||
assign_bd_address -offset 0x001200000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] -force
|
||||
assign_bd_address -offset 0x0010000A0000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_core/Reg] -force
|
||||
assign_bd_address -offset 0x0010000A8000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] -force
|
||||
assign_bd_address -offset 0x001000080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] -force
|
||||
assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] -force
|
||||
assign_bd_address -offset 0x001000156000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000150000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000151000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000153000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000152000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000100000 -range 0x00040000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_LPS_OCM] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_LPS_OCM] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_LPS_OCM] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force
|
||||
assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] -force
|
||||
|
||||
# Exclude Address Segments
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S/SEG_inst_zynq_ps_HPC1_LPS_OCM]
|
||||
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM/SEG_inst_zynq_ps_HPC1_LPS_OCM]
|
||||
|
||||
create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM
|
||||
exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_SG/SEG_inst_zynq_ps_HPC1_LPS_OCM]
|
||||
|
||||
exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM]
|
||||
exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM]
|
||||
exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM]
|
||||
|
||||
|
||||
# Restore current instance
|
||||
|
||||
@@ -14,10 +14,10 @@ $(IP_XGE_PCS_PMA_EXAMPLE_SRCS)
|
||||
IP_XGE_PCS_PMA_HDL_SIM_SRCS = $(IP_DIR)/xge_pcs_pma/model_10gbe.sv \
|
||||
$(wildcard $(addprefix $(IP_BUILD_DIR)/xge_pcs_pma/, \
|
||||
xge_pcs_pma.v \
|
||||
hdl/xxv_ethernet_v3_0_vl_rfs.sv \
|
||||
hdl/xxv_ethernet_v4_0_vl_rfs.sv \
|
||||
ip_0/hdl/*.v \
|
||||
ip_0/sim/*.v \
|
||||
xxv_ethernet_v3_0_1/*.v \
|
||||
xxv_ethernet_v4_0_0/*.v \
|
||||
))
|
||||
|
||||
IP_XGE_PCS_PMA_EXAMPLE_SRCS = \
|
||||
@@ -25,13 +25,7 @@ $(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_common_wrapper.v \
|
||||
$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_gt_gtye4_common_wrapper.v \
|
||||
$(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/gtwizard_ultrascale_v1_7_gtye4_common.v \
|
||||
|
||||
# Describe the paths for the patch file, the file to be patched, and the
|
||||
# patched copy of the file.
|
||||
IP_XGE_FILE_PATCH = $(IP_DIR)/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch
|
||||
IP_XGE_FILE_TO_PATCH = $(IP_BUILD_DIR)/xge_pcs_pma/xxv_ethernet_v3_0_1/xge_pcs_pma_wrapper.v
|
||||
IP_XGE_PATCHED_FILE = $(IP_BUILD_DIR)/xge_pcs_pma_wrapper.v.patched
|
||||
|
||||
IP_XGE_PCS_PMA_SRCS = $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_PATCHED_FILE)
|
||||
IP_XGE_PCS_PMA_SRCS = $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_BUILD_DIR)/xge_pcs_pma/xxv_ethernet_v4_0_0/xge_pcs_pma_wrapper.v
|
||||
|
||||
IP_XGE_PCS_PMA_OUTS = \
|
||||
$(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci.out \
|
||||
@@ -43,9 +37,5 @@ $(IP_XGE_PCS_PMA_EXAMPLE_SRCS) : $(IP_XGE_PCS_PMA_OUTS)
|
||||
$(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS): IP_XGE_PCS_PMA_TRGT
|
||||
@:
|
||||
|
||||
IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_FILE_PATCH)
|
||||
IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci
|
||||
$(call BUILD_VIVADO_IP,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1)
|
||||
cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_FILE_TO_PATCH).orig
|
||||
cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_PATCHED_FILE)
|
||||
patch $(IP_XGE_PATCHED_FILE) $(IP_XGE_FILE_PATCH)
|
||||
$(call REBUILD_VIVADO_IP_WITH_PATCH,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0,$(call RESOLVE_PATH,$(IP_XGE_PATCHED_FILE)),$(call RESOLVE_PATH,$(IP_XGE_FILE_TO_PATCH)))
|
||||
|
||||
@@ -55,11 +55,10 @@ module ten_gige_phy (
|
||||
wire a_gt_reset_tx_done, gt_reset_tx_done;
|
||||
wire a_gt_reset_rx_done, gt_reset_rx_done;
|
||||
|
||||
wire stat_rx_status_tmp;
|
||||
reg stat_rx_status;
|
||||
wire stat_rx_status;
|
||||
|
||||
reg [RX_RST_COUNT_W-1:0] rst_count;
|
||||
reg gt_rx_reset_in;
|
||||
// reg [RX_RST_COUNT_W-1:0] rst_count;
|
||||
// reg gt_rx_reset_in;
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Xilinx 10G/25G IP High Speed Ethernet Subsystem Instance
|
||||
@@ -141,7 +140,7 @@ module ten_gige_phy (
|
||||
.gt_reset_rx_done_out_0 (a_gt_reset_rx_done),
|
||||
.gt_reset_all_in_0 (areset),
|
||||
.gt_tx_reset_in_0 (1'b0),
|
||||
.gt_rx_reset_in_0 (gt_rx_reset_in),
|
||||
.gt_rx_reset_in_0 (1'b0),
|
||||
.rx_reset_0 (rx_reset),
|
||||
.rx_mii_d_0 (xgmii_rxd),
|
||||
.rx_mii_c_0 (xgmii_rxc),
|
||||
@@ -154,7 +153,7 @@ module ten_gige_phy (
|
||||
.stat_rx_local_fault_0 (),
|
||||
.stat_rx_block_lock_0 (),
|
||||
.stat_rx_valid_ctrl_code_0 (),
|
||||
.stat_rx_status_0 (stat_rx_status_tmp), // rx_core_clk_0 domain
|
||||
.stat_rx_status_0 (stat_rx_status), // rx_core_clk_0 domain
|
||||
.stat_rx_hi_ber_0 (),
|
||||
.stat_rx_bad_code_0 (),
|
||||
.stat_rx_bad_code_valid_0 (),
|
||||
@@ -172,7 +171,9 @@ module ten_gige_phy (
|
||||
.ctl_tx_test_pattern_seed_a_0 (58'b0),
|
||||
.ctl_tx_test_pattern_seed_b_0 (58'b0),
|
||||
.ctl_tx_prbs31_test_pattern_enable_0 (1'b0),
|
||||
.gt_loopback_in_0 (3'b0)
|
||||
.gt_loopback_in_0 (3'b0),
|
||||
.gt_txelecidle_0 (1'b0),
|
||||
.gt_drprst_0 (1'b0)
|
||||
);
|
||||
|
||||
|
||||
@@ -233,42 +234,4 @@ module ten_gige_phy (
|
||||
.out (rx_reset)
|
||||
);
|
||||
|
||||
// This state machine resets the RX GT part of the core periodically when
|
||||
// the link is down. This is necessary due to a bug in the Xilinx IP.
|
||||
always @(posedge xgmii_clk, posedge areset) begin
|
||||
if (areset) begin
|
||||
gt_rx_reset_in <= 0;
|
||||
rst_count <= 0;
|
||||
stat_rx_status <= 0;
|
||||
end else begin
|
||||
stat_rx_status <= stat_rx_status_tmp;
|
||||
|
||||
// Periodically reset until link is up
|
||||
if (!stat_rx_status) begin
|
||||
rst_count <= rst_count + 1;
|
||||
|
||||
if (!gt_rx_reset_in) begin
|
||||
// We're not in reset. Wait until RX_RST_WAIT cycles have elapsed,
|
||||
// then reset.
|
||||
if (rst_count == RX_RST_WAIT-1) begin
|
||||
rst_count <= 0;
|
||||
gt_rx_reset_in <= 1;
|
||||
end
|
||||
end else begin
|
||||
// We're in reset. Wait until RX_RST_DURATION cycles have elapsed
|
||||
// before deasserting reset.
|
||||
if (rst_count == RX_RST_DURATION-1) begin
|
||||
rst_count <= 0;
|
||||
gt_rx_reset_in <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// Currently linked, so all is well
|
||||
end else begin
|
||||
rst_count <= 0;
|
||||
gt_rx_reset_in <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -7,24 +7,28 @@
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>xge_pcs_pma</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xxv_ethernet" spirit:version="3.0"/>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xxv_ethernet" spirit:version="4.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_CLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_RESET_PORT_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_RESET_PORT_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AN_RESET_PORT_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
@@ -37,7 +41,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_0.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -50,7 +54,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_1.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -63,7 +67,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_2.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -76,7 +80,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_3.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -89,7 +93,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_0.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -102,7 +106,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_1.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -115,7 +119,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_2.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -128,7 +132,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_EXP_3.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -141,7 +145,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_0.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -154,7 +158,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_1.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -167,7 +171,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_2.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -180,7 +184,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_RX_PREEMPT_3.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -193,7 +197,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_0.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -206,7 +210,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_1.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -219,7 +223,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_2.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -232,7 +236,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_3.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -245,7 +249,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_0.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -258,7 +262,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_1.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -271,7 +275,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_2.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -284,7 +288,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_EXP_3.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -297,7 +301,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_0.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -310,7 +314,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_1.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -323,7 +327,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_2.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -336,7 +340,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXIS_TX_PREEMPT_3.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
@@ -356,8 +360,9 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DRP_CLK_PORT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_RX_DATAPATH_0_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_RX_DATAPATH_1_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GTWIZ_RESET_RX_DATAPATH_2_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
@@ -370,26 +375,30 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRPCLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_DONE_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_DONE_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_DRP_DONE_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
@@ -397,8 +406,9 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REFCLK_OUT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REF_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RESET_ALL_IN_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
@@ -417,21 +427,25 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_RESET_IN_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_RESET_IN_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_RESET_IN_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_0.RX_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_1.RX_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_2.RX_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_RX_SERDES_INTERFACE_3.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
@@ -442,21 +456,25 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_RESET_IN_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_RESET_IN_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_RESET_IN_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_0.TX_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_1.TX_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_2.TX_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.ADDITIONAL_QUAD_SETTINGS">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.CHNL_NUMBER">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.GT_DIRECTION">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.GT_TX_SERDES_INTERFACE_3.MASTERCLK_SRC">undef</spirit:configurableElementValue>
|
||||
@@ -465,113 +483,142 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MII_MAC_TX_CLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0CLK_IN_PORT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0REFCLK_IN_PORT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL0_RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1CLK_IN_PORT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1REFCLK_IN_PORT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLL1_RESET_PORT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QPLLRESET_IN_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RXRECCLKOUT_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_CORE_CLK_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_CLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_RESET_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_RESET_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_MAC_MII_RESET_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
@@ -580,14 +627,26 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_RESET_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.FREQ_HZ">156.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.FREQ_HZ">156250000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.FREQ_HZ">156.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.FREQ_HZ">156250000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.FREQ_HZ">156.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.FREQ_HZ">156250000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.FREQ_HZ">156.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.FREQ_HZ">156250000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.PARENT_ID">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_CLK_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_RESET_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_RESET_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RX_SERDES_RESET_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
@@ -616,7 +675,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_0.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -647,7 +706,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_1.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -678,7 +737,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_2.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -709,7 +768,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
@@ -719,124 +778,156 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_3.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_CLOCK3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_SIGNAL_RESETN3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_CORE_CLK_3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK0_OUT_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_OUT_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK90_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_CLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MAC_MII_RESET_3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT0.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT2.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_MII_CLK_PORT3.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PORT0.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PORT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.TX_RESET_PORT2.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
@@ -855,9 +946,11 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BASE_R_KR">BASE-R</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCKING">Asynchronous</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CMAC_CORE_SELECT">CMACE4_X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_PATH_INTERFACE">MII</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_DATAPATH_PARITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_GT_BOARD_INTERFACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PIPELINE_REG">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PREEMPTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_PREEMPTION_FIFO">0</spirit:configurableElementValue>
|
||||
@@ -867,6 +960,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY_CHK">zynquplus</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAST_SIM_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GTM_GROUP_SELECT">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_DIFFCTRL_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_DRP_CLK">100.00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GT_GROUP_SELECT">Quad X0Y0</spirit:configurableElementValue>
|
||||
@@ -881,7 +975,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_SHARED_LOGIC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_STATISTICS_COUNTERS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_USER_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INS_LOSS_NYQ">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INS_LOSS_NYQ">30</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE1_GT_LOC">X0Y16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE2_GT_LOC">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LANE3_GT_LOC">NA</spirit:configurableElementValue>
|
||||
@@ -896,19 +990,23 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_EQ_MODE">AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATISTICS_REGS_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SWITCH_1_10_25G">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYS_CLK">4000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_LATENCY_ADJUST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_TOTAL_BYTES_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XGMII_INTERFACE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_BOARD_PROJECT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.VERSAL_GT_BOARD_FLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADD_GT_CNTRL_STS_PORTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ANLT_CLK_IN_MHZ">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BASE_R_KR">BASE-R</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCKING">Asynchronous</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CMAC_CORE_SELECT">CMACE4_X0Y0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CORE">Ethernet PCS/PMA 64-bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xge_pcs_pma</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_PATH_INTERFACE">MII</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFFCLK_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DATAPATH_PARITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_GT_BOARD_INTERFACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PIPELINE_REG">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PREEMPTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PREEMPTION_FIFO">0</spirit:configurableElementValue>
|
||||
@@ -918,6 +1016,7 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VLANE_ADJUST_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ETHERNET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FAST_SIM_MODE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GTM_GROUP_SELECT">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_DRP_CLK">100.00</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_GROUP_SELECT">Quad_X0Y4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_LOCATION">1</spirit:configurableElementValue>
|
||||
@@ -962,12 +1061,12 @@
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
@@ -1177,6 +1276,73 @@
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LANE1_GT_LOC" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LINE_RATE" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"ctl_rx_data_pattern_select_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_rx_prbs31_test_pattern_enable_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_rx_test_pattern_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_rx_test_pattern_enable_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_tx_data_pattern_select_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_tx_prbs31_test_pattern_enable_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_tx_test_pattern_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_tx_test_pattern_enable_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"ctl_tx_test_pattern_seed_a_0":[{"direction":"in","physical_left":"57"
|
||||
,"physical_right":"0","is_vector":"true"}],"ctl_tx_test_pattern_seed_b_0":[{"direction":"in","physical_left":"57","physical_right":"0","is_vector":"true"}],"ctl_tx_test_pattern_select_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"dclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_dmonitorout_0":[{"direction":"out","physical_left":"16","physical_right":"0","is_vector":"true"}],"gt_drpaddr_0":[{"direction":"in","physical_left":"9","physical_right":"0","is_vector":"true"}],"gt_drpclk_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_drpdi_0":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"gt_drpdo_0":[{"direction":"out","physical_left":"15","physical_right":"0","is_vector":"true"}],"gt_drpen_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_drprdy_0":[{"direction":"out","physical_left":"0","physic
|
||||
al_right":"0","is_vector":"false"}],"gt_drprst_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_drpwe_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_eyescandataerror_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_eyescanreset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_eyescantrigger_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_loopback_in_0":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"gt_pcsrsvdin_0":[{"direction":"in","physical_left":"15","physical_right":"0","is_vector":"true"}],"gt_reset_all_in_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_reset_rx_done_out_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_reset_tx_done_out_0":[{"direction":"out","phys
|
||||
ical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rx_reset_in_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxbufreset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxbufstatus_0":[{"direction":"out","physical_left":"2","physical_right":"0","is_vector":"true"}],"gt_rxcdrhold_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxcommadeten_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxdfeagchold_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxdfelpmreset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxlatclk_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxlpmen_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxn_in_0":[{"direction":"in","phys
|
||||
ical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxp_in_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxpcsreset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxpmareset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxpolarity_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxprbscntreset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxprbserr_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxprbssel_0":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"gt_rxrate_0":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"gt_rxslide_in_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_rxstartofseq_0":[{"direction":"out","physica
|
||||
l_left":"1","physical_right":"0","is_vector":"true"}],"gt_tx_reset_in_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txbufstatus_0":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"gt_txdiffctrl_0":[{"direction":"in","physical_left":"4","physical_right":"0","is_vector":"true"}],"gt_txelecidle_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txinhibit_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txlatclk_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txmaincursor_0":[{"direction":"in","physical_left":"6","physical_right":"0","is_vector":"true"}],"gt_txn_out_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txp_out_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txpcsreset_0":[{"direction":"in","physical_lef
|
||||
t":"0","physical_right":"0","is_vector":"false"}],"gt_txpmareset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txpolarity_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txpostcursor_0":[{"direction":"in","physical_left":"4","physical_right":"0","is_vector":"true"}],"gt_txprbsforceerr_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gt_txprbssel_0":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"gt_txprecursor_0":[{"direction":"in","physical_left":"4","physical_right":"0","is_vector":"true"}],"gtpowergood_out_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"gtwiz_reset_qpll0lock_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gtwiz_reset_qpll0reset_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"gtwiz_reset_qpll1lock
|
||||
_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"gtwiz_reset_qpll1reset_out":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"qpll0clk_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll0refclk_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1clk_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"qpll1refclk_in":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"true"}],"rx_clk_out_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"rx_core_clk_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rx_mii_c_0":[{"direction":"out","physical_left":"7","physical_right":"0","is_vector":"true"}],"rx_mii_d_0":[{"direction":"out","physical_left":"63","physical_right":"0","is_vector":"true"}],"rx_reset_0":[{"direction":
|
||||
"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rx_serdes_reset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"rxoutclksel_in_0":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}],"rxrecclkout_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_bad_code_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_bad_code_valid_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_block_lock_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_error_0":[{"direction":"out","physical_left":"7","physical_right":"0","is_vector":"true"}],"stat_rx_error_valid_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_fifo_error_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"
|
||||
}],"stat_rx_framing_err_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_framing_err_valid_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_hi_ber_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_local_fault_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_status_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_rx_valid_ctrl_code_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"stat_tx_local_fault_0":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"sys_reset":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"tx_mii_c_0":[{"direction":"in","physical_left":"7","physical_right":"0","is_vector":"true"}],"tx_mii_clk_0":[{"direction":"out","physical_left":"0","phy
|
||||
sical_right":"0","is_vector":"false"}],"tx_mii_d_0":[{"direction":"in","physical_left":"63","physical_right":"0","is_vector":"true"}],"tx_reset_0":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"txoutclksel_in_0":[{"direction":"in","physical_left":"2","physical_right":"0","is_vector":"true"}]},"interfaces":{"ctl_rx_0":{"vlnv":"xilinx.com:display_xxv_ethernet:ctrl_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:ctrl_ports:2.0","mode":"slave","parameters":{},"port_maps":{"ctl_rx_check_preamble":[{"physical_name":"ctl_rx_check_preamble_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_check_sfd":[{"physical_name":"ctl_rx_check_sfd_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_custom_preamble_enable":[{"physical_name":"ctl_rx_custom_preamble_enable_0","physical_left":"0","physical_right":"0","logical
|
||||
_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_data_pattern_select":[{"physical_name":"ctl_rx_data_pattern_select_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_delete_fcs":[{"physical_name":"ctl_rx_delete_fcs_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_enable":[{"physical_name":"ctl_rx_enable_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_force_resync":[{"physical_name":"ctl_rx_force_resync_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_ignore_fcs":[{"physical_name":"ctl_rx_ignore_fcs_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_max_packet_len":[{"physical_name":"ctl_rx_max_packet_len_0","physical_left":"14","physical
|
||||
_right":"0","logical_left":"14","logical_right":"0","port_maps_used":"none"}],"ctl_rx_min_packet_len":[{"physical_name":"ctl_rx_min_packet_len_0","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"ctl_rx_prbs31_test_pattern_enable":[{"physical_name":"ctl_rx_prbs31_test_pattern_enable_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_process_lfi":[{"physical_name":"ctl_rx_process_lfi_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_test_pattern":[{"physical_name":"ctl_rx_test_pattern_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ctl_rx_test_pattern_enable":[{"physical_name":"ctl_rx_test_pattern_enable_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"drp_clk_port":{"vlnv":"x
|
||||
ilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"sys_reset","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","us
|
||||
age":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"dclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"gt_drp_ports_0":{"vlnv":"xilinx.com:interface:drp:1.0","abstraction_type":"xilinx.com:interface:drp_rtl:1.0","mode":"slave","parameters":{},"port_maps":{"DADDR":[{"physical_name":"gt_drpaddr_0","physical_left":"9","physical_right":"0","logical_left":"9","logical_right":"0","port_maps_used":"none"}],"DEN":[{"physical_name":"gt_drpen_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"
|
||||
0","port_maps_used":"none"}],"DI":[{"physical_name":"gt_drpdi_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"DO":[{"physical_name":"gt_drpdo_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"DRDY":[{"physical_name":"gt_drprdy_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"DWE":[{"physical_name":"gt_drpwe_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"gt_drpclk_port0":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_per
|
||||
mission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage"
|
||||
:"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"gt_drpclk_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"gt_reset_rx_done_out_0":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"gt_reset_rx_done_out_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"gt_reset_tx_done_out_0":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"
|
||||
xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"gt_reset_tx_done_out_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"gt_rx":{"vlnv":"xilinx.com:display_xxv_ethernet:gt_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:gt_ports:2.0","mode":"slave","parameters":{},"port_maps":{"gt_port_0_n":[{"physical_name":"gt_rxn_in_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_0_p":[{"physical_name":"gt_rxp_in_0","physical
|
||||
_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_1_n":[{"physical_name":"gt_rxn_in_1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_1_p":[{"physical_name":"gt_rxp_in_1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_2_n":[{"physical_name":"gt_rxn_in_2","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_2_p":[{"physical_name":"gt_rxp_in_2","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_3_n":[{"physical_name":"gt_rxn_in_3","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_3_p":[{"physical_name":"gt_rxp_in_3","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used"
|
||||
:"none"}]}},"gt_trans_debug_0":{"vlnv":"xilinx.com:display_xxv_ethernet:drp_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:drp_ports:2.0","mode":"slave","parameters":{},"port_maps":{"gt_dmonitorout":[{"physical_name":"gt_dmonitorout_0","physical_left":"16","physical_right":"0","logical_left":"16","logical_right":"0","port_maps_used":"none"}],"gt_eyescandataerror":[{"physical_name":"gt_eyescandataerror_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_eyescanreset":[{"physical_name":"gt_eyescanreset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_eyescantrigger":[{"physical_name":"gt_eyescantrigger_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_pcsrsvdin":[{"physical_name":"gt_pcsrsvdin_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port
|
||||
_maps_used":"none"}],"gt_rxbufreset":[{"physical_name":"gt_rxbufreset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxbufstatus":[{"physical_name":"gt_rxbufstatus_0","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"gt_rxcdrhold":[{"physical_name":"gt_rxcdrhold_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxcommadeten":[{"physical_name":"gt_rxcommadeten_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxdfeagchold":[{"physical_name":"gt_rxdfeagchold_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxdfelpmreset":[{"physical_name":"gt_rxdfelpmreset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxlatclk":[{
|
||||
"physical_name":"gt_rxlatclk_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxlpmen":[{"physical_name":"gt_rxlpmen_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxpcsreset":[{"physical_name":"gt_rxpcsreset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxpmareset":[{"physical_name":"gt_rxpmareset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxpolarity":[{"physical_name":"gt_rxpolarity_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxprbscntreset":[{"physical_name":"gt_rxprbscntreset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxprbserr":[{"physical_name":"gt_rxprbserr_0","physical_left":"0"
|
||||
,"physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxprbssel":[{"physical_name":"gt_rxprbssel_0","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"gt_rxrate":[{"physical_name":"gt_rxrate_0","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"gt_rxslide_in":[{"physical_name":"gt_rxslide_in_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_rxstartofseq":[{"physical_name":"gt_rxstartofseq_0","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"gt_txbufstatus":[{"physical_name":"gt_txbufstatus_0","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"gt_txdiffctrl":[{"physical_name":"gt_txdiffctrl_0","physical_left":"4","physical_right":"0","logical_left":"4","logical_right
|
||||
":"0","port_maps_used":"none"}],"gt_txinhibit":[{"physical_name":"gt_txinhibit_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_txlatclk":[{"physical_name":"gt_txlatclk_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_txmaincursor":[{"physical_name":"gt_txmaincursor_0","physical_left":"6","physical_right":"0","logical_left":"6","logical_right":"0","port_maps_used":"none"}],"gt_txpcsreset":[{"physical_name":"gt_txpcsreset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_txpmareset":[{"physical_name":"gt_txpmareset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_txpolarity":[{"physical_name":"gt_txpolarity_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_txpostcursor":[{"
|
||||
physical_name":"gt_txpostcursor_0","physical_left":"4","physical_right":"0","logical_left":"4","logical_right":"0","port_maps_used":"none"}],"gt_txprbsforceerr":[{"physical_name":"gt_txprbsforceerr_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_txprbssel":[{"physical_name":"gt_txprbssel_0","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"gt_txprecursor":[{"physical_name":"gt_txprecursor_0","physical_left":"4","physical_right":"0","logical_left":"4","logical_right":"0","port_maps_used":"none"}]}},"gt_tx":{"vlnv":"xilinx.com:display_xxv_ethernet:gt_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:gt_ports:2.0","mode":"master","parameters":{},"port_maps":{"gt_port_0_n":[{"physical_name":"gt_txn_out_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_0_p":[{"physical_name":"gt_txp_out
|
||||
_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_1_n":[{"physical_name":"gt_txn_out_1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_1_p":[{"physical_name":"gt_txp_out_1","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_2_n":[{"physical_name":"gt_txn_out_2","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_2_p":[{"physical_name":"gt_txp_out_2","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_3_n":[{"physical_name":"gt_txn_out_3","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gt_port_3_p":[{"physical_name":"gt_txp_out_3","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"
|
||||
0","port_maps_used":"none"}]}},"mii_rx_0":{"vlnv":"xilinx.com:display_xxv_ethernet:user_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:user_int_ports:2.0","mode":"master","parameters":{},"port_maps":{"rx_mii_c":[{"physical_name":"rx_mii_c_0","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"rx_mii_d":[{"physical_name":"rx_mii_d_0","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}]}},"mii_tx_0":{"vlnv":"xilinx.com:display_xxv_ethernet:user_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:user_int_ports:2.0","mode":"slave","parameters":{},"port_maps":{"tx_mii_c":[{"physical_name":"tx_mii_c_0","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"tx_mii_d":[{"physical_name":"tx_mii_d_0","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"n
|
||||
one"}]}},"qpll0_reset_port":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"gtwiz_reset_qpll0reset_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"qpll0clk_in_port":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferre
|
||||
d":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0",
|
||||
"value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"qpll0clk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"qpll0refclk_in_port":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is
|
||||
_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"qpll0refclk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"qpll1_reset_port":{"vlnv":"xilinx.com:signal:reset:1.0","abstrac
|
||||
tion_type":"xilinx.com:signal:reset_rtl:1.0","mode":"master","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"gtwiz_reset_qpll1reset_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"qpll1clk_in_port":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_
|
||||
src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated"
|
||||
,"format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"qpll1clk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"qpll1refclk_in_port":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"defau
|
||||
lt","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"qpll1refclk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"rx_clk_port0":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"AS
|
||||
SOCIATED_BUSIF":[{"value":"mii_rx_0","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"user_rx_reset_0","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"390625000","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src
|
||||
":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"rx_clk_out_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"rx_core_clk_0":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"axis_rx_0:axis_rx_exp_0:axis_rx_preempt_0","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none"
|
||||
,"is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CL
|
||||
K":[{"physical_name":"rx_core_clk_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"rx_reset_port0":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"rx_reset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"rx_serdes_reset_port0":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value
|
||||
_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"rx_serdes_reset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"rxrecclkout_0":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":
|
||||
true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name
|
||||
":"rxrecclkout_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"shared_logic":{"vlnv":"xilinx.com:display_xxv_ethernet:shared_logic_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:shared_logic_ports:2.0","mode":"slave","parameters":{},"port_maps":{"gtwiz_reset_qpll0lock_in":[{"physical_name":"gtwiz_reset_qpll0lock_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gtwiz_reset_qpll0reset_out":[{"physical_name":"gtwiz_reset_qpll0reset_out","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gtwiz_reset_qpll1lock_in":[{"physical_name":"gtwiz_reset_qpll1lock_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"gtwiz_reset_qpll1reset_out":[{"physical_name":"gtwiz_reset_qpll1reset_out","physical_left":"0","physical_right":"0","logical_left"
|
||||
:"0","logical_right":"0","port_maps_used":"none"}],"qpll0clk_in":[{"physical_name":"qpll0clk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"qpll0refclk_in":[{"physical_name":"qpll0refclk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"qpll1clk_in":[{"physical_name":"qpll1clk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"qpll1refclk_in":[{"physical_name":"qpll1refclk_in","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"stat_rx_0":{"vlnv":"xilinx.com:display_xxv_ethernet:statistics_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_ethernet:statistics_ports:2.0","mode":"master","parameters":{},"port_maps":{"stat_rx_bad_code":[{"physical_name":"stat_rx_bad_code_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_r
|
||||
ight":"0","port_maps_used":"none"}],"stat_rx_bad_code_valid":[{"physical_name":"stat_rx_bad_code_valid_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_bad_fcs":[{"physical_name":"stat_rx_bad_fcs_0","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"stat_rx_bad_preamble":[{"physical_name":"stat_rx_bad_preamble_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_bad_sfd":[{"physical_name":"stat_rx_bad_sfd_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_block_lock":[{"physical_name":"stat_rx_block_lock_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_broadcast":[{"physical_name":"stat_rx_broadcast_0","physical_left":"0","physical_right":"0","logical_left":"0","lo
|
||||
gical_right":"0","port_maps_used":"none"}],"stat_rx_error":[{"physical_name":"stat_rx_error_0","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"stat_rx_error_valid":[{"physical_name":"stat_rx_error_valid_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_fifo_error":[{"physical_name":"stat_rx_fifo_error_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_fragment":[{"physical_name":"stat_rx_fragment_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_framing_err":[{"physical_name":"stat_rx_framing_err_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_framing_err_valid":[{"physical_name":"stat_rx_framing_err_valid_0","physical_left":"0","physical_right":"0","logical_
|
||||
left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_got_signal_os":[{"physical_name":"stat_rx_got_signal_os_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_hi_ber":[{"physical_name":"stat_rx_hi_ber_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_inrangeerr":[{"physical_name":"stat_rx_inrangeerr_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_internal_local_fault":[{"physical_name":"stat_rx_internal_local_fault_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_jabber":[{"physical_name":"stat_rx_jabber_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_local_fault":[{"physical_name":"stat_rx_local_fault_0","physical_left":"0","physical
|
||||
_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_multicast":[{"physical_name":"stat_rx_multicast_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_oversize":[{"physical_name":"stat_rx_oversize_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_1024_1518_bytes":[{"physical_name":"stat_rx_packet_1024_1518_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_128_255_bytes":[{"physical_name":"stat_rx_packet_128_255_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_1519_1522_bytes":[{"physical_name":"stat_rx_packet_1519_1522_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_1523
|
||||
_1548_bytes":[{"physical_name":"stat_rx_packet_1523_1548_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_1549_2047_bytes":[{"physical_name":"stat_rx_packet_1549_2047_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_2048_4095_bytes":[{"physical_name":"stat_rx_packet_2048_4095_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_256_511_bytes":[{"physical_name":"stat_rx_packet_256_511_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_4096_8191_bytes":[{"physical_name":"stat_rx_packet_4096_8191_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_512_1023_bytes":[{"physical_name":"stat_rx_pack
|
||||
et_512_1023_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_64_bytes":[{"physical_name":"stat_rx_packet_64_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_65_127_bytes":[{"physical_name":"stat_rx_packet_65_127_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_8192_9215_bytes":[{"physical_name":"stat_rx_packet_8192_9215_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_bad_fcs":[{"physical_name":"stat_rx_packet_bad_fcs_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_packet_large":[{"physical_name":"stat_rx_packet_large_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right
|
||||
":"0","port_maps_used":"none"}],"stat_rx_packet_small":[{"physical_name":"stat_rx_packet_small_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause":[{"physical_name":"stat_rx_pause_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta0":[{"physical_name":"stat_rx_pause_quanta0_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta1":[{"physical_name":"stat_rx_pause_quanta1_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta2":[{"physical_name":"stat_rx_pause_quanta2_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta3":[{"physical_name":"stat_rx_pause_quanta3_0","physical_left":"15","physical_right":"0"
|
||||
,"logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta4":[{"physical_name":"stat_rx_pause_quanta4_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta5":[{"physical_name":"stat_rx_pause_quanta5_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta6":[{"physical_name":"stat_rx_pause_quanta6_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta7":[{"physical_name":"stat_rx_pause_quanta7_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_quanta8":[{"physical_name":"stat_rx_pause_quanta8_0","physical_left":"15","physical_right":"0","logical_left":"15","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_req":[{"physical_name":"stat_rx_pause
|
||||
_req_0","physical_left":"8","physical_right":"0","logical_left":"8","logical_right":"0","port_maps_used":"none"}],"stat_rx_pause_valid":[{"physical_name":"stat_rx_pause_valid_0","physical_left":"8","physical_right":"0","logical_left":"8","logical_right":"0","port_maps_used":"none"}],"stat_rx_received_local_fault":[{"physical_name":"stat_rx_received_local_fault_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_remote_fault":[{"physical_name":"stat_rx_remote_fault_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_stomped_fcs":[{"physical_name":"stat_rx_stomped_fcs_0","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"stat_rx_test_pattern_mismatch":[{"physical_name":"stat_rx_test_pattern_mismatch_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"non
|
||||
e"}],"stat_rx_toolong":[{"physical_name":"stat_rx_toolong_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_total_bytes":[{"physical_name":"stat_rx_total_bytes_0","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"stat_rx_total_good_bytes":[{"physical_name":"stat_rx_total_good_bytes_0","physical_left":"13","physical_right":"0","logical_left":"13","logical_right":"0","port_maps_used":"none"}],"stat_rx_total_good_packets":[{"physical_name":"stat_rx_total_good_packets_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_total_packets":[{"physical_name":"stat_rx_total_packets_0","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"stat_rx_truncated":[{"physical_name":"stat_rx_truncated_0","physical_left":"0","physical_right":"0","logical_left":"0","l
|
||||
ogical_right":"0","port_maps_used":"none"}],"stat_rx_undersize":[{"physical_name":"stat_rx_undersize_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_unicast":[{"physical_name":"stat_rx_unicast_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_user_pause":[{"physical_name":"stat_rx_user_pause_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_valid_ctrl_code":[{"physical_name":"stat_rx_valid_ctrl_code_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_rx_vlan":[{"physical_name":"stat_rx_vlan_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"stat_tx_0":{"vlnv":"xilinx.com:display_xxv_ethernet:statistics_ports_int:2.0","abstraction_type":"xilinx.com:display_xxv_e
|
||||
thernet:statistics_ports:2.0","mode":"master","parameters":{},"port_maps":{"stat_tx_bad_fcs":[{"physical_name":"stat_tx_bad_fcs_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_broadcast":[{"physical_name":"stat_tx_broadcast_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_fifo_error":[{"physical_name":"stat_tx_fifo_error_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_frame_error":[{"physical_name":"stat_tx_frame_error_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_local_fault":[{"physical_name":"stat_tx_local_fault_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_multicast":[{"physical_name":"stat_tx_multicast_0","physical_left":"0","physica
|
||||
l_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_1024_1518_bytes":[{"physical_name":"stat_tx_packet_1024_1518_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_128_255_bytes":[{"physical_name":"stat_tx_packet_128_255_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_1519_1522_bytes":[{"physical_name":"stat_tx_packet_1519_1522_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_1523_1548_bytes":[{"physical_name":"stat_tx_packet_1523_1548_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_1549_2047_bytes":[{"physical_name":"stat_tx_packet_1549_2047_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_ri
|
||||
ght":"0","port_maps_used":"none"}],"stat_tx_packet_2048_4095_bytes":[{"physical_name":"stat_tx_packet_2048_4095_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_256_511_bytes":[{"physical_name":"stat_tx_packet_256_511_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_4096_8191_bytes":[{"physical_name":"stat_tx_packet_4096_8191_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_512_1023_bytes":[{"physical_name":"stat_tx_packet_512_1023_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_64_bytes":[{"physical_name":"stat_tx_packet_64_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_65_127_b
|
||||
ytes":[{"physical_name":"stat_tx_packet_65_127_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_8192_9215_bytes":[{"physical_name":"stat_tx_packet_8192_9215_bytes_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_large":[{"physical_name":"stat_tx_packet_large_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_packet_small":[{"physical_name":"stat_tx_packet_small_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_pause":[{"physical_name":"stat_tx_pause_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_pause_valid":[{"physical_name":"stat_tx_pause_valid_0","physical_left":"8","physical_right":"0","logical_left":"8","logical_right":"0"
|
||||
,"port_maps_used":"none"}],"stat_tx_total_bytes":[{"physical_name":"stat_tx_total_bytes_0","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"stat_tx_total_good_bytes":[{"physical_name":"stat_tx_total_good_bytes_0","physical_left":"13","physical_right":"0","logical_left":"13","logical_right":"0","port_maps_used":"none"}],"stat_tx_total_good_packets":[{"physical_name":"stat_tx_total_good_packets_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_total_packets":[{"physical_name":"stat_tx_total_packets_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_unicast":[{"physical_name":"stat_tx_unicast_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_user_pause":[{"physical_name":"stat_tx_user_pause_0","physical_left":"0","physical_right":"
|
||||
0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"stat_tx_vlan":[{"physical_name":"stat_tx_vlan_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"sys_reset_port":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"sys_reset","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"tx_clk_port0":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_
|
||||
rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"axis_tx_0:mii_tx_0:axis_tx_exp_0:axis_tx_preempt_0","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_RESET":[{"value":"user_tx_reset_0","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"390625000","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is
|
||||
_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"tx_clk_out_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"tx_mii_clk_port0":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"master","parameters":{"ASSOCIATED_BUSIF":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"user_tx_reset_0","value_src":"constant","value_permission":"us
|
||||
er","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"390625000","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"long","usage":"all","is_ips_inferred":false,"is_static_object":true}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_i
|
||||
ps_inferred":true,"is_static_object":false}]},"port_maps":{"CLK":[{"physical_name":"tx_mii_clk_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"tx_reset_port0":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_HIGH","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"tx_reset_0","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}}}}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
|
||||
@@ -1,30 +0,0 @@
|
||||
692a693,712
|
||||
>
|
||||
> //---------------------------------------------------------------------------
|
||||
> // Workaround for link status bug. See SR 10471238 for details.
|
||||
> //---------------------------------------------------------------------------
|
||||
>
|
||||
> reg [13:0] rx_clk_noctrlcode_count;
|
||||
>
|
||||
> always @(posedge rx_core_clk_0) begin
|
||||
> if (rx_reset_done_0 == 1'b1) begin
|
||||
> rx_clk_noctrlcode_count <= 14'h270F;
|
||||
> end else begin
|
||||
> if (stat_rx_valid_ctrl_code_0 == 1'b1) begin
|
||||
> rx_clk_noctrlcode_count <= 14'h270F;
|
||||
> end else begin
|
||||
> rx_clk_noctrlcode_count <= rx_clk_noctrlcode_count - 1;
|
||||
> end
|
||||
> end
|
||||
> end
|
||||
>
|
||||
> //---------------------------------------------------------------------------
|
||||
700c720,725
|
||||
< if(stat_rx_block_lock_0 == 1'b0)
|
||||
---
|
||||
> //------------------------------------------------------------------------
|
||||
> // Workaround for link status bug. See SR 10471238 for details.
|
||||
> // Original code: if(stat_rx_block_lock_0 == 1'b0)
|
||||
> // New code:
|
||||
> if(stat_rx_block_lock_0 == 1'b0 || rx_clk_noctrlcode_count ==14'h0)
|
||||
> //------------------------------------------------------------------------
|
||||
@@ -5,8 +5,8 @@
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
VIVADO_VER=2019.1
|
||||
VIVADO_VER_FULL=2019.1.1_AR73068
|
||||
VIVADO_VER=2021.1
|
||||
VIVADO_VER_FULL=2021.1
|
||||
DISPLAY_NAME="USRP-X4xx"
|
||||
REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd)
|
||||
|
||||
|
||||
@@ -579,7 +579,7 @@ module x4xx_qsfp_wrapper_tb #(
|
||||
end
|
||||
repeat (4) axi.rd(LANE_BASE+REG_MAC_LSB,data);
|
||||
|
||||
if (MGT_PROTOCOL == `MGT_100GbE && !USE_MAC) begin
|
||||
if ((MGT_PROTOCOL == `MGT_100GbE && !USE_MAC) || (MGT_PROTOCOL == `MGT_10GbE && USE_MAC)) begin
|
||||
reg_link_up = 1;
|
||||
end
|
||||
|
||||
@@ -592,7 +592,8 @@ module x4xx_qsfp_wrapper_tb #(
|
||||
else axi.rd(LANE_BASE+REG_MAC_CTRL_STATUS,32'h0000_0080);
|
||||
else assert(1);
|
||||
|
||||
axi.rd(LANE_BASE+REG_PHY_CTRL_STATUS,0);
|
||||
|
||||
axi.rd(LANE_BASE+REG_PHY_CTRL_STATUS,(MGT_PROTOCOL == `MGT_10GbE && USE_MAC) ? reg_link_up : 0);
|
||||
// en 0 / value 1
|
||||
axi.rd(LANE_BASE+REG_MAC_LED_CTL,0);
|
||||
// enabled with value 0
|
||||
|
||||
Reference in New Issue
Block a user