From 1b952d33df2bfc8ffdc2413e537a3cefb7cee341 Mon Sep 17 00:00:00 2001 From: Sam O'Brien Date: Wed, 30 Mar 2022 10:56:17 -0500 Subject: [PATCH] fpga: x400: Upgrade to Vivado 2021.1 Commit includes: - Upgrade x400-specific IP - Removal of xge_pcs_pma IP patch Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55 --- top/x400/ip/adc_100m_bd/adc_100m_bd.tcl | 61 ++- top/x400/ip/adc_400m_bd/adc_400m_bd.tcl | 63 ++- .../axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci | 43 ++- top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl | 37 +- .../axi_inter_2x128_512_bd.tcl | 36 +- .../axi_inter_4x64_512_bd.tcl | 314 +++++++++++++-- .../axi_interconnect_app_bd.tcl | 36 +- .../axi_interconnect_dma_bd.tcl | 42 +- .../axi_interconnect_eth_bd.tcl | 66 ++-- top/x400/ip/dac_100m_bd/dac_100m_bd.tcl | 55 ++- top/x400/ip/dac_400m_bd/dac_400m_bd.tcl | 61 ++- top/x400/ip/ddr4_64bits/ddr4_64bits.xci | 56 ++- top/x400/ip/eth_100g_bd/Makefile.inc | 2 +- top/x400/ip/eth_100g_bd/eth_100g.sv | 22 +- top/x400/ip/eth_100g_bd/eth_100g_bd.tcl | 46 +-- top/x400/ip/eth_100g_bd/lbus_tb/Makefile | 6 +- top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci | 35 +- .../ip/fifo_short_2clk/fifo_short_2clk.xci | 35 +- top/x400/ip/hb47_1to2/hb47_1to2.xci | 47 ++- top/x400/ip/hb47_2to1/hb47_2to1.xci | 63 ++- .../ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl | 250 ++++++------ top/x400/ip/xge_pcs_pma/Makefile.inc | 18 +- top/x400/ip/xge_pcs_pma/ten_gige_phy.v | 53 +-- top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci | 362 +++++++++++++----- .../xge_pcs_pma/xge_pcs_pma_wrapper.v.patch | 30 -- top/x400/setupenv.sh | 4 +- .../x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv | 5 +- 27 files changed, 1156 insertions(+), 692 deletions(-) delete mode 100644 top/x400/ip/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch diff --git a/top/x400/ip/adc_100m_bd/adc_100m_bd.tcl b/top/x400/ip/adc_100m_bd/adc_100m_bd.tcl index a3fcc6e..6670eea 100644 --- a/top/x400/ip/adc_100m_bd/adc_100m_bd.tcl +++ b/top/x400/ip/adc_100m_bd/adc_100m_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -83,10 +83,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -107,11 +107,11 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } @@ -119,10 +119,10 @@ if { ${design_name} eq "" } { # Add USER_COMMENTS on $design_name set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name] -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -139,7 +139,7 @@ xilinx.com:ip:fir_compiler:7.2\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -149,7 +149,7 @@ xilinx.com:ip:fir_compiler:7.2\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } @@ -168,7 +168,7 @@ scale_2x\ " set list_mods_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." foreach mod_vlnv $list_check_mods { if { [can_resolve_reference $mod_vlnv] == 0 } { @@ -177,14 +177,14 @@ scale_2x\ } if { $list_mods_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -208,14 +208,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -263,34 +263,29 @@ proc create_root_design { parentCell } { # Create ports set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ] - set data_clk [ create_bd_port -dir I -type clk data_clk ] + set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {adc_data_out} \ - CONFIG.FREQ_HZ {122880000} \ ] $data_clk set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ] set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ] set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ] - set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] + set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {adc_i_data_in:adc_q_data_in} \ CONFIG.ASSOCIATED_RESET {adc_gearbox_resetn_rclk:rfdc_adc_axi_resetn_rclk} \ - CONFIG.FREQ_HZ {184320000} \ ] $rfdc_clk - set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {368640000} \ - ] $rfdc_clk_2x + set rfdc_clk_2x [ create_bd_port -dir I -type clk -freq_hz 368640000 rfdc_clk_2x ] set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ] # Create instance: adc_3_1_clk_converter_0, and set properties set block_name adc_3_1_clk_converter set block_cell_name adc_3_1_clk_converter_0 if { [catch {set adc_3_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $adc_3_1_clk_converter_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -306,10 +301,10 @@ proc create_root_design { parentCell } { set block_name adc_gearbox_2x1 set block_cell_name adc_gearbox_2x1_0 if { [catch {set adc_gearbox_2x1_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $adc_gearbox_2x1_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -334,10 +329,10 @@ proc create_root_design { parentCell } { set block_name ddc_saturate set block_cell_name ddc_saturate if { [catch {set ddc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $ddc_saturate eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -345,7 +340,7 @@ proc create_root_design { parentCell } { set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ] set_property -dict [ list \ CONFIG.Clock_Frequency {384} \ - CONFIG.CoefficientVector {-2,0,8,12,0,-26,-36,0,63,81,0,-130,-161,0,241,291,0,-415,-491,0,676,788,0,-1059,-1223,0,1621,1864,0,-2473,-2860,0,3892,4607,0,-6820,-8705,0,17900,36048,43690,36048,17900,0,-8705,-6820,0,4607,3892,0,-2860,-2473,0,1864,1621,0,-1223,-1059,0,788,676,0,-491,-415,0,291,241,0,-161,-130,0,81,63,0,-36,-26,0,12,8,0,-2} \ + CONFIG.CoefficientVector {-2,0,8,12,0,-26,-36,0,63,81,0,-130,-161,0,241,291,0,-415,-491,0,676,788,0,-1059,-1223,0,1621,1864,0,-2473,-2860,0,3892,4607,0,-6820,-8705,0,17900,36048,43690,36048,17900,0,-8705,-6820,0,4607,3892,0,-2860,-2473,0,1864,1621,0,-1223,-1059,0,788,676,0,-491,-415,0,291,241,0,-161,-130,0,81,63,0,-36,-26,0,12,8,0,-2}\ CONFIG.Coefficient_Fractional_Bits {0} \ CONFIG.Coefficient_Sets {1} \ CONFIG.Coefficient_Sign {Signed} \ @@ -376,10 +371,10 @@ proc create_root_design { parentCell } { set block_name scale_2x set block_cell_name scale_2x_0 if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $scale_2x_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } set_property -dict [ list \ diff --git a/top/x400/ip/adc_400m_bd/adc_400m_bd.tcl b/top/x400/ip/adc_400m_bd/adc_400m_bd.tcl index 59ed949..1b7a355 100644 --- a/top/x400/ip/adc_400m_bd/adc_400m_bd.tcl +++ b/top/x400/ip/adc_400m_bd/adc_400m_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -83,10 +83,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -107,11 +107,11 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } @@ -119,10 +119,10 @@ if { ${design_name} eq "" } { # Add USER_COMMENTS on $design_name set_property USER_COMMENTS.comment_0 "Scale_2x is a simple shift to left by 2 logic and does not need any pipeline stage" [get_bd_designs $design_name] -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -139,7 +139,7 @@ xilinx.com:ip:fir_compiler:7.2\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -149,7 +149,7 @@ xilinx.com:ip:fir_compiler:7.2\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } @@ -168,7 +168,7 @@ scale_2x\ " set list_mods_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." foreach mod_vlnv $list_check_mods { if { [can_resolve_reference $mod_vlnv] == 0 } { @@ -177,14 +177,14 @@ scale_2x\ } if { $list_mods_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -208,14 +208,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -263,22 +263,17 @@ proc create_root_design { parentCell } { # Create ports set adc_data_out_resetn_dclk [ create_bd_port -dir I -type rst adc_data_out_resetn_dclk ] - set data_clk [ create_bd_port -dir I -type clk data_clk ] + set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_RESET {adc_data_out_resetn_dclk} \ - CONFIG.FREQ_HZ {122880000} \ ] $data_clk set enable_data_to_fir_rclk [ create_bd_port -dir I enable_data_to_fir_rclk ] set fir_resetn_rclk2x [ create_bd_port -dir I -type rst fir_resetn_rclk2x ] set rfdc_adc_axi_resetn_rclk [ create_bd_port -dir I -type rst rfdc_adc_axi_resetn_rclk ] - set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ - ] $rfdc_clk - set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ] + set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ] + set rfdc_clk_2x [ create_bd_port -dir I -type clk -freq_hz 368640000 rfdc_clk_2x ] set_property -dict [ list \ CONFIG.ASSOCIATED_RESET {fir_resetn_rclk2x} \ - CONFIG.FREQ_HZ {368640000} \ ] $rfdc_clk_2x set swap_iq_2x [ create_bd_port -dir I swap_iq_2x ] @@ -294,10 +289,10 @@ proc create_root_design { parentCell } { set block_name adc_gearbox_2x4 set block_cell_name adc_gearbox_2x4_0 if { [catch {set adc_gearbox_2x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $adc_gearbox_2x4_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -305,10 +300,10 @@ proc create_root_design { parentCell } { set block_name adc_gearbox_8x4 set block_cell_name adc_gearbox_8x4_0 if { [catch {set adc_gearbox_8x4_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $adc_gearbox_8x4_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -333,10 +328,10 @@ proc create_root_design { parentCell } { set block_name ddc_400m_saturate set block_cell_name ddc_400m_saturate_0 if { [catch {set ddc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $ddc_400m_saturate_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -344,13 +339,13 @@ proc create_root_design { parentCell } { set fir_compiler_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir_compiler_0 ] set_property -dict [ list \ CONFIG.Clock_Frequency {384} \ - CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2} \ + CONFIG.CoefficientVector {2,5,0,-13,-20,0,40,55,0,-95,-121,0,191,236,0,-351,-422,0,599,708,0,-974,-1136,0,1534,1778,0,-2392,-2783,0,3825,4547,0,-6775,-8668,0,17881,36039,43691,36039,17881,0,-8668,-6775,0,4547,3825,0,-2783,-2392,0,1778,1534,0,-1136,-974,0,708,599,0,-422,-351,0,236,191,0,-121,-95,0,55,40,0,-20,-13,0,5,2}\ CONFIG.Coefficient_Fractional_Bits {0} \ CONFIG.Coefficient_Sets {1} \ CONFIG.Coefficient_Sign {Signed} \ CONFIG.Coefficient_Structure {Inferred} \ CONFIG.Coefficient_Width {18} \ - CONFIG.ColumnConfig {26} \ + CONFIG.ColumnConfig {13} \ CONFIG.Decimation_Rate {3} \ CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ CONFIG.Filter_Type {Decimation} \ @@ -372,10 +367,10 @@ proc create_root_design { parentCell } { set block_name scale_2x set block_cell_name scale_2x_0 if { [catch {set scale_2x_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $scale_2x_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } set_property -dict [ list \ diff --git a/top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci b/top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci index 26d7060..15add59 100644 --- a/top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci +++ b/top/x400/ip/axi64_4k_2clk_fifo/axi64_4k_2clk_fifo.xci @@ -13,13 +13,15 @@ 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 1 0 0 @@ -43,7 +45,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -59,7 +61,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -68,12 +70,14 @@ 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 1 0 @@ -98,7 +102,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -114,7 +118,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -123,8 +127,9 @@ 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -509,12 +514,12 @@ TRUE TRUE IP_Flow - 4 + 5 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -577,6 +582,22 @@ + + + diff --git a/top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl b/top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl index da97912..4e06552 100644 --- a/top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl +++ b/top/x400/ip/axi_eth_dma_bd/axi_eth_dma_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -128,7 +128,7 @@ xilinx.com:ip:smartconnect:1.0\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -138,14 +138,14 @@ xilinx.com:ip:smartconnect:1.0\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -169,14 +169,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -252,11 +252,10 @@ proc create_root_design { parentCell } { # Create ports - set clk40 [ create_bd_port -dir I -type clk clk40 ] + set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {e2c:axi_eth_dma:axi_hp:c2e} \ CONFIG.ASSOCIATED_RESET {clk40_rstn} \ - CONFIG.FREQ_HZ {40000000} \ ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] set eth_rx_irq [ create_bd_port -dir O -type intr eth_rx_irq ] @@ -301,10 +300,10 @@ proc create_root_design { parentCell } { connect_bd_net -net clk40_rstn [get_bd_ports clk40_rstn] [get_bd_pins axi_eth_dma/axi_resetn] [get_bd_pins smartconnect_eth_dma/aresetn] # Create address segments - create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_SG] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg - create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_MM2S] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg - create_bd_addr_seg -range 0x001000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma/Data_S2MM] [get_bd_addr_segs axi_hp/Reg] SEG_m_axi_to_ps_Reg - create_bd_addr_seg -range 0x010000000000 -offset 0x00000000 [get_bd_addr_spaces axi_eth_dma] [get_bd_addr_segs axi_eth_dma/S_AXI_LITE/Reg] SEG_axi_eth_dma_Reg + assign_bd_address -offset 0x00000000 -range 0x001000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma/Data_SG] [get_bd_addr_segs axi_hp/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x001000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma/Data_MM2S] [get_bd_addr_segs axi_hp/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x001000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma/Data_S2MM] [get_bd_addr_segs axi_hp/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x010000000000 -target_address_space [get_bd_addr_spaces axi_eth_dma] [get_bd_addr_segs axi_eth_dma/S_AXI_LITE/Reg] -force # Restore current instance diff --git a/top/x400/ip/axi_inter_2x128_512_bd/axi_inter_2x128_512_bd.tcl b/top/x400/ip/axi_inter_2x128_512_bd/axi_inter_2x128_512_bd.tcl index 0c30985..8b9c490 100644 --- a/top/x400/ip/axi_inter_2x128_512_bd/axi_inter_2x128_512_bd.tcl +++ b/top/x400/ip/axi_inter_2x128_512_bd/axi_inter_2x128_512_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } { " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } { } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -167,14 +167,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -264,21 +264,19 @@ proc create_root_design { parentCell } { # Create ports - set M0_AXI_ACLK [ create_bd_port -dir I -type clk M0_AXI_ACLK ] + set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {M0_AXI} \ CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \ - CONFIG.FREQ_HZ {350000000} \ ] $M0_AXI_ACLK set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ] set_property -dict [ list \ CONFIG.POLARITY {ACTIVE_LOW} \ ] $M0_AXI_ARESETN - set S0_AXI_ACLK [ create_bd_port -dir I -type clk S0_AXI_ACLK ] + set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI} \ CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN:S0_AXI_ARESETN} \ - CONFIG.FREQ_HZ {350000000} \ ] $S0_AXI_ACLK set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ] @@ -307,8 +305,8 @@ proc create_root_design { parentCell } { connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] # Create address segments - create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg - create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force # Restore current instance diff --git a/top/x400/ip/axi_inter_4x64_512_bd/axi_inter_4x64_512_bd.tcl b/top/x400/ip/axi_inter_4x64_512_bd/axi_inter_4x64_512_bd.tcl index c99f085..fb79809 100644 --- a/top/x400/ip/axi_inter_4x64_512_bd/axi_inter_4x64_512_bd.tcl +++ b/top/x400/ip/axi_inter_4x64_512_bd/axi_inter_4x64_512_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,11 +100,11 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } @@ -113,10 +113,10 @@ if { ${design_name} eq "" } { set_property USER_COMMENTS.comment_0 "Note 1: The ID width of the AXI interconnect (xbar) master changes depending on the axi_interconnect optimization strategy. It will be zero for 'minimize area' and non-zero for 'maximize performance'. Note 2: I have explicitly set ID width to 1 on the input ports to match our AXI master and to 4 on the output block to match the DRAM slave." [get_bd_designs $design_name] -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -133,7 +133,7 @@ xilinx.com:ip:axi_register_slice:2.1\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -143,14 +143,14 @@ xilinx.com:ip:axi_register_slice:2.1\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -174,14 +174,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -226,7 +226,6 @@ proc create_root_design { parentCell } { CONFIG.NUM_READ_THREADS {1} \ CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PHASE {0.000} \ CONFIG.PROTOCOL {AXI4} \ CONFIG.READ_WRITE_MODE {READ_WRITE} \ CONFIG.RUSER_BITS_PER_BYTE {0} \ @@ -259,7 +258,6 @@ proc create_root_design { parentCell } { CONFIG.NUM_READ_THREADS {1} \ CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PHASE {0.000} \ CONFIG.PROTOCOL {AXI4} \ CONFIG.READ_WRITE_MODE {READ_WRITE} \ CONFIG.RUSER_BITS_PER_BYTE {0} \ @@ -292,7 +290,6 @@ proc create_root_design { parentCell } { CONFIG.NUM_READ_THREADS {1} \ CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PHASE {0.000} \ CONFIG.PROTOCOL {AXI4} \ CONFIG.READ_WRITE_MODE {READ_WRITE} \ CONFIG.RUSER_BITS_PER_BYTE {0} \ @@ -325,7 +322,6 @@ proc create_root_design { parentCell } { CONFIG.NUM_READ_THREADS {1} \ CONFIG.NUM_WRITE_OUTSTANDING {2} \ CONFIG.NUM_WRITE_THREADS {1} \ - CONFIG.PHASE {0.000} \ CONFIG.PROTOCOL {AXI4} \ CONFIG.READ_WRITE_MODE {READ_WRITE} \ CONFIG.RUSER_BITS_PER_BYTE {0} \ @@ -337,21 +333,19 @@ proc create_root_design { parentCell } { # Create ports - set M0_AXI_ACLK [ create_bd_port -dir I -type clk M0_AXI_ACLK ] + set M0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 M0_AXI_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {M0_AXI} \ CONFIG.ASSOCIATED_RESET {M0_AXI_ARESETN} \ - CONFIG.FREQ_HZ {350000000} \ ] $M0_AXI_ACLK set M0_AXI_ARESETN [ create_bd_port -dir I -type rst M0_AXI_ARESETN ] set_property -dict [ list \ CONFIG.POLARITY {ACTIVE_LOW} \ ] $M0_AXI_ARESETN - set S0_AXI_ACLK [ create_bd_port -dir I -type clk S0_AXI_ACLK ] + set S0_AXI_ACLK [ create_bd_port -dir I -type clk -freq_hz 350000000 S0_AXI_ACLK ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {S0_AXI:S1_AXI:S2_AXI:S3_AXI} \ CONFIG.ASSOCIATED_RESET {S0_AXI_ARESETN} \ - CONFIG.FREQ_HZ {350000000} \ ] $S0_AXI_ACLK set S0_AXI_ARESETN [ create_bd_port -dir I -type rst S0_AXI_ARESETN ] @@ -360,6 +354,276 @@ proc create_root_design { parentCell } { set_property -dict [ list \ CONFIG.DATA_WIDTH {256} \ CONFIG.ID_WIDTH {4} \ + CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A00_ADDR_WIDTH {0} \ + CONFIG.M01_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A00_ADDR_WIDTH {0} \ + CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A00_ADDR_WIDTH {0} \ + CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A00_ADDR_WIDTH {0} \ + CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A00_ADDR_WIDTH {0} \ + CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A00_ADDR_WIDTH {0} \ + CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A00_ADDR_WIDTH {0} \ + CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A00_ADDR_WIDTH {0} \ + CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A00_ADDR_WIDTH {0} \ + CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A00_ADDR_WIDTH {0} \ + CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A00_ADDR_WIDTH {0} \ + CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A00_ADDR_WIDTH {0} \ + CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A00_ADDR_WIDTH {0} \ + CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A00_ADDR_WIDTH {0} \ + CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A00_ADDR_WIDTH {0} \ + CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \ CONFIG.NUM_MI {1} \ CONFIG.NUM_SI {4} \ CONFIG.S01_BASE_ID {0x00000004} \ @@ -549,10 +813,10 @@ proc create_root_design { parentCell } { connect_bd_net -net S0_AXI_ARESETN_1 [get_bd_ports S0_AXI_ARESETN] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins axi_dwidth_converter_0/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_1/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_2/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_3/s_axi_aresetn] [get_bd_pins axi_dwidth_converter_4/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins axi_register_slice_1/aresetn] [get_bd_pins axi_register_slice_2/aresetn] [get_bd_pins axi_register_slice_3/aresetn] [get_bd_pins axi_register_slice_4/aresetn] [get_bd_pins axi_register_slice_5/aresetn] [get_bd_pins axi_register_slice_6/aresetn] [get_bd_pins axi_register_slice_7/aresetn] [get_bd_pins axi_register_slice_8/aresetn] # Create address segments - create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg - create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M00_AXI_Reg - create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M0_AXI_Reg - create_bd_addr_seg -range 0x000100000000 -offset 0x00000000 [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] SEG_M0_AXI_Reg + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S0_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S1_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S2_AXI] [get_bd_addr_segs M0_AXI/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces S3_AXI] [get_bd_addr_segs M0_AXI/Reg] -force # Restore current instance diff --git a/top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl b/top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl index 6647aa3..edf0440 100644 --- a/top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl +++ b/top/x400/ip/axi_interconnect_app_bd/axi_interconnect_app_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } { " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } { } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -167,14 +167,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -189,7 +189,6 @@ proc create_root_design { parentCell } { set m_axi_qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp0 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -206,7 +205,6 @@ proc create_root_design { parentCell } { set m_axi_qsfp1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_qsfp1 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -227,7 +225,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BRESP {1} \ @@ -256,12 +253,11 @@ proc create_root_design { parentCell } { # Create ports - set clk40 [ create_bd_port -dir I -type clk clk40 ] + set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {m_axi_qsfp0:m_axi_qsfp1:s_axi_app} \ CONFIG.ASSOCIATED_RESET {clk40_rstn} \ CONFIG.CLK_DOMAIN {axi_interconnect_app_bd_clk40} \ - CONFIG.FREQ_HZ {40000000} \ ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] @@ -281,8 +277,8 @@ proc create_root_design { parentCell } { connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] # Create address segments - create_bd_addr_seg -range 0x00040000 -offset 0x001200000000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp0/Reg] SEG_m_axi_qsfp0_Reg - create_bd_addr_seg -range 0x00040000 -offset 0x001200040000 [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp1/Reg] SEG_m_axi_qsfp1_Reg + assign_bd_address -offset 0x001200000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp0/Reg] -force + assign_bd_address -offset 0x001200040000 -range 0x00040000 -target_address_space [get_bd_addr_spaces s_axi_app] [get_bd_addr_segs m_axi_qsfp1/Reg] -force # Restore current instance diff --git a/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl b/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl index 43c959a..5dd381b 100644 --- a/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl +++ b/top/x400/ip/axi_interconnect_dma_bd/axi_interconnect_dma_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } { " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } { } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -167,14 +167,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -189,7 +189,6 @@ proc create_root_design { parentCell } { set m_axi_hp [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_hp ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {49} \ - CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ CONFIG.DATA_WIDTH {128} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {1} \ @@ -210,7 +209,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ CONFIG.DATA_WIDTH {128} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BRESP {1} \ @@ -243,7 +241,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ CONFIG.DATA_WIDTH {128} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BRESP {1} \ @@ -276,7 +273,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ CONFIG.DATA_WIDTH {128} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BRESP {1} \ @@ -309,7 +305,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ CONFIG.DATA_WIDTH {128} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BRESP {1} \ @@ -338,12 +333,11 @@ proc create_root_design { parentCell } { # Create ports - set clk40 [ create_bd_port -dir I -type clk clk40 ] + set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {s_axi_hp_dma0:s_axi_hp_dma1:s_axi_hp_dma2:s_axi_hp_dma3:m_axi_hp} \ CONFIG.ASSOCIATED_RESET {clk40_rstn} \ CONFIG.CLK_DOMAIN {axi_interconnect_dma_bd_clk40} \ - CONFIG.FREQ_HZ {40000000} \ ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] @@ -381,10 +375,10 @@ proc create_root_design { parentCell } { connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins axi_interconnect_0/S02_ARESETN] [get_bd_pins axi_interconnect_0/S03_ARESETN] # Create address segments - create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma0] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg - create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma1] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg - create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma2] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg - create_bd_addr_seg -range 0x0002000000000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp_dma3] [get_bd_addr_segs m_axi_hp/Reg] SEG_m_axi_hp_Reg + assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma0] [get_bd_addr_segs m_axi_hp/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma1] [get_bd_addr_segs m_axi_hp/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma2] [get_bd_addr_segs m_axi_hp/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x0002000000000000 -target_address_space [get_bd_addr_spaces s_axi_hp_dma3] [get_bd_addr_segs m_axi_hp/Reg] -force # Restore current instance diff --git a/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl b/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl index 2efa50b..a288793 100644 --- a/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl +++ b/top/x400/ip/axi_interconnect_eth_bd/axi_interconnect_eth_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -126,7 +126,7 @@ if { $bCheckIPs == 1 } { " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -136,14 +136,14 @@ if { $bCheckIPs == 1 } { } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -167,14 +167,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -189,7 +189,6 @@ proc create_root_design { parentCell } { set m_axi_dma0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma0 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -203,7 +202,6 @@ proc create_root_design { parentCell } { set m_axi_dma1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma1 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -217,7 +215,6 @@ proc create_root_design { parentCell } { set m_axi_dma2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma2 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -231,7 +228,6 @@ proc create_root_design { parentCell } { set m_axi_dma3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_dma3 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -245,7 +241,6 @@ proc create_root_design { parentCell } { set m_axi_mac0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac0 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -262,7 +257,6 @@ proc create_root_design { parentCell } { set m_axi_mac1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac1 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -276,7 +270,6 @@ proc create_root_design { parentCell } { set m_axi_mac2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac2 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -290,7 +283,6 @@ proc create_root_design { parentCell } { set m_axi_mac3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mac3 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -304,7 +296,6 @@ proc create_root_design { parentCell } { set m_axi_misc0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc0 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -321,7 +312,6 @@ proc create_root_design { parentCell } { set m_axi_misc1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc1 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -335,7 +325,6 @@ proc create_root_design { parentCell } { set m_axi_misc2 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc2 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -349,7 +338,6 @@ proc create_root_design { parentCell } { set m_axi_misc3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_misc3 ] set_property -dict [ list \ CONFIG.ADDR_WIDTH {40} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BURST {0} \ @@ -366,7 +354,6 @@ proc create_root_design { parentCell } { CONFIG.ARUSER_WIDTH {0} \ CONFIG.AWUSER_WIDTH {0} \ CONFIG.BUSER_WIDTH {0} \ - CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ CONFIG.DATA_WIDTH {32} \ CONFIG.FREQ_HZ {40000000} \ CONFIG.HAS_BRESP {1} \ @@ -395,12 +382,11 @@ proc create_root_design { parentCell } { # Create ports - set clk40 [ create_bd_port -dir I -type clk clk40 ] + set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {m_axi_misc0:m_axi_mac0:s_axi_eth:m_axi_misc3:m_axi_mac3:m_axi_dma1:m_axi_misc1:m_axi_mac2:m_axi_dma2:m_axi_mac1:m_axi_misc2:m_axi_dma0:m_axi_dma3} \ CONFIG.ASSOCIATED_RESET {clk40_rstn} \ CONFIG.CLK_DOMAIN {axi_interconnect_eth_bd_clk40} \ - CONFIG.FREQ_HZ {40000000} \ ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] @@ -430,18 +416,18 @@ proc create_root_design { parentCell } { connect_bd_net -net clk40_rstn_1 [get_bd_ports clk40_rstn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins axi_interconnect_0/M06_ARESETN] [get_bd_pins axi_interconnect_0/M07_ARESETN] [get_bd_pins axi_interconnect_0/M08_ARESETN] [get_bd_pins axi_interconnect_0/M09_ARESETN] [get_bd_pins axi_interconnect_0/M10_ARESETN] [get_bd_pins axi_interconnect_0/M11_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] # Create address segments - create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] SEG_m_axi_dma0_Reg - create_bd_addr_seg -range 0x00008000 -offset 0x00010000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] SEG_m_axi_dma1_Reg - create_bd_addr_seg -range 0x00008000 -offset 0x00020000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] SEG_m_axi_dma2_Reg - create_bd_addr_seg -range 0x00008000 -offset 0x00030000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] SEG_m_axi_dma3_Reg - create_bd_addr_seg -range 0x00002000 -offset 0x0000C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] SEG_m_axi_mac0_Reg - create_bd_addr_seg -range 0x00002000 -offset 0x0001C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] SEG_m_axi_mac1_Reg - create_bd_addr_seg -range 0x00002000 -offset 0x0002C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] SEG_m_axi_mac2_Reg - create_bd_addr_seg -range 0x00002000 -offset 0x0003C000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] SEG_m_axi_mac3_Reg - create_bd_addr_seg -range 0x00004000 -offset 0x00008000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] SEG_m_axi_misc0_Reg - create_bd_addr_seg -range 0x00004000 -offset 0x00018000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] SEG_m_axi_misc1_Reg - create_bd_addr_seg -range 0x00004000 -offset 0x00028000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] SEG_m_axi_misc2_Reg - create_bd_addr_seg -range 0x00004000 -offset 0x00038000 [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] SEG_m_axi_misc3_Reg + assign_bd_address -offset 0x00000000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma0/Reg] -force + assign_bd_address -offset 0x00010000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma1/Reg] -force + assign_bd_address -offset 0x00020000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma2/Reg] -force + assign_bd_address -offset 0x00030000 -range 0x00008000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_dma3/Reg] -force + assign_bd_address -offset 0x0000C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac0/Reg] -force + assign_bd_address -offset 0x0001C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac1/Reg] -force + assign_bd_address -offset 0x0002C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac2/Reg] -force + assign_bd_address -offset 0x0003C000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_mac3/Reg] -force + assign_bd_address -offset 0x00008000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc0/Reg] -force + assign_bd_address -offset 0x00018000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc1/Reg] -force + assign_bd_address -offset 0x00028000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc2/Reg] -force + assign_bd_address -offset 0x00038000 -range 0x00004000 -target_address_space [get_bd_addr_spaces s_axi_eth] [get_bd_addr_segs m_axi_misc3/Reg] -force # Restore current instance diff --git a/top/x400/ip/dac_100m_bd/dac_100m_bd.tcl b/top/x400/ip/dac_100m_bd/dac_100m_bd.tcl index fcc30e5..65bfcc7 100644 --- a/top/x400/ip/dac_100m_bd/dac_100m_bd.tcl +++ b/top/x400/ip/dac_100m_bd/dac_100m_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -83,10 +83,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -107,19 +107,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -137,7 +137,7 @@ xilinx.com:ip:axis_register_slice:1.1\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -147,7 +147,7 @@ xilinx.com:ip:axis_register_slice:1.1\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } @@ -165,7 +165,7 @@ duc_saturate\ " set list_mods_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." foreach mod_vlnv $list_check_mods { if { [can_resolve_reference $mod_vlnv] == 0 } { @@ -174,14 +174,14 @@ duc_saturate\ } if { $list_mods_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -205,14 +205,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -248,22 +248,19 @@ proc create_root_design { parentCell } { set dac_data_in_resetn_dclk [ create_bd_port -dir I -type rst dac_data_in_resetn_dclk ] set dac_data_in_resetn_rclk [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk ] set dac_data_in_resetn_rclk2x [ create_bd_port -dir I -type rst dac_data_in_resetn_rclk2x ] - set data_clk [ create_bd_port -dir I -type clk data_clk ] + set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {dac_data_in} \ CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk} \ - CONFIG.FREQ_HZ {122880000} \ ] $data_clk - set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] + set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {dac_data_out} \ CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk} \ - CONFIG.FREQ_HZ {184320000} \ ] $rfdc_clk - set rfdc_clk_2x [ create_bd_port -dir I -type clk rfdc_clk_2x ] + set rfdc_clk_2x [ create_bd_port -dir I -type clk -freq_hz 368640000 rfdc_clk_2x ] set_property -dict [ list \ CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_rclk2x} \ - CONFIG.FREQ_HZ {368640000} \ ] $rfdc_clk_2x # Create instance: constant_high, and set properties @@ -273,10 +270,10 @@ proc create_root_design { parentCell } { set block_name dac_1_3_clk_converter set block_cell_name dac_1_3_clk_converter_0 if { [catch {set dac_1_3_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $dac_1_3_clk_converter_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -284,10 +281,10 @@ proc create_root_design { parentCell } { set block_name dac_2_1_clk_converter set block_cell_name dac_2_1_clk_converter_0 if { [catch {set dac_2_1_clk_converter_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $dac_2_1_clk_converter_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -295,7 +292,7 @@ proc create_root_design { parentCell } { set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ] set_property -dict [ list \ CONFIG.Clock_Frequency {368.64} \ - CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \ + CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7}\ CONFIG.Coefficient_Fractional_Bits {0} \ CONFIG.Coefficient_Sets {1} \ CONFIG.Coefficient_Sign {Signed} \ @@ -333,10 +330,10 @@ proc create_root_design { parentCell } { set block_name duc_saturate set block_cell_name duc_saturate if { [catch {set duc_saturate [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $duc_saturate eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } diff --git a/top/x400/ip/dac_400m_bd/dac_400m_bd.tcl b/top/x400/ip/dac_400m_bd/dac_400m_bd.tcl index 96392ad..93a2481 100644 --- a/top/x400/ip/dac_400m_bd/dac_400m_bd.tcl +++ b/top/x400/ip/dac_400m_bd/dac_400m_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -83,10 +83,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -107,19 +107,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -134,7 +134,7 @@ xilinx.com:ip:fir_compiler:7.2\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -144,7 +144,7 @@ xilinx.com:ip:fir_compiler:7.2\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } @@ -162,7 +162,7 @@ duc_400m_saturate\ " set list_mods_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." foreach mod_vlnv $list_check_mods { if { [can_resolve_reference $mod_vlnv] == 0 } { @@ -171,14 +171,14 @@ duc_400m_saturate\ } if { $list_mods_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -202,14 +202,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -232,28 +232,21 @@ proc create_root_design { parentCell } { set dac_data_out_tdata [ create_bd_port -dir O -from 255 -to 0 -type data dac_data_out_tdata ] set dac_data_out_tready [ create_bd_port -dir I -type data dac_data_out_tready ] set dac_data_out_tvalid [ create_bd_port -dir O -type data dac_data_out_tvalid ] - set data_clk [ create_bd_port -dir I -type clk data_clk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {122880000} \ - ] $data_clk - set data_clk_2x [ create_bd_port -dir I -type clk data_clk_2x ] + set data_clk [ create_bd_port -dir I -type clk -freq_hz 122880000 data_clk ] + set data_clk_2x [ create_bd_port -dir I -type clk -freq_hz 245760000 data_clk_2x ] set_property -dict [ list \ CONFIG.ASSOCIATED_RESET {dac_data_in_resetn_dclk2x} \ - CONFIG.FREQ_HZ {245760000} \ ] $data_clk_2x - set rfdc_clk [ create_bd_port -dir I -type clk rfdc_clk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {184320000} \ - ] $rfdc_clk + set rfdc_clk [ create_bd_port -dir I -type clk -freq_hz 184320000 rfdc_clk ] # Create instance: dac_gearbox_4x2_0, and set properties set block_name dac_gearbox_4x2 set block_cell_name dac_gearbox_4x2_0 if { [catch {set dac_gearbox_4x2_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $dac_gearbox_4x2_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -261,10 +254,10 @@ proc create_root_design { parentCell } { set block_name dac_gearbox_6x8 set block_cell_name dac_gearbox_6x8_0 if { [catch {set dac_gearbox_6x8_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $dac_gearbox_6x8_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -272,13 +265,13 @@ proc create_root_design { parentCell } { set dac_interpolator [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 dac_interpolator ] set_property -dict [ list \ CONFIG.Clock_Frequency {245.76} \ - CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7} \ + CONFIG.CoefficientVector {-7,0,24,37,0,-78,-107,0,189,244,0,-389,-484,0,723,873,0,-1245,-1473,0,2029,2364,0,-3177,-3668,0,4862,5592,0,-7418,-8579,0,11675,13820,0,-20461,-26115,0,53699,108144,131069,108144,53699,0,-26115,-20461,0,13820,11675,0,-8579,-7418,0,5592,4862,0,-3668,-3177,0,2364,2029,0,-1473,-1245,0,873,723,0,-484,-389,0,244,189,0,-107,-78,0,37,24,0,-7}\ CONFIG.Coefficient_Fractional_Bits {0} \ CONFIG.Coefficient_Sets {1} \ CONFIG.Coefficient_Sign {Signed} \ CONFIG.Coefficient_Structure {Inferred} \ CONFIG.Coefficient_Width {18} \ - CONFIG.ColumnConfig {27} \ + CONFIG.ColumnConfig {14} \ CONFIG.Decimation_Rate {1} \ CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ CONFIG.Filter_Type {Interpolation} \ @@ -300,10 +293,10 @@ proc create_root_design { parentCell } { set block_name duc_400m_saturate set block_cell_name duc_400m_saturate_0 if { [catch {set duc_400m_saturate_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $duc_400m_saturate_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } diff --git a/top/x400/ip/ddr4_64bits/ddr4_64bits.xci b/top/x400/ip/ddr4_64bits/ddr4_64bits.xci index 42a73fb..4bafe03 100644 --- a/top/x400/ip/ddr4_64bits/ddr4_64bits.xci +++ b/top/x400/ip/ddr4_64bits/ddr4_64bits.xci @@ -12,18 +12,22 @@ + 0 0 + 0 0 + 0 0 + 0 0 TDM 8 @@ -41,6 +45,7 @@ 1250 0 + 0 0 0 32 @@ -65,7 +70,7 @@ 1 2 1 - 0.000 + 0.0 AXI4 READ_WRITE 0 @@ -95,7 +100,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -109,8 +114,9 @@ 100000000 + 0 0 - 0.000 + 0.0 0 29 512 @@ -155,6 +161,7 @@ 8 8 64 + false 0 1.2V false @@ -174,6 +181,7 @@ DDR4_750_Timing 0 0 + ROW_COLUMN_BANK 1 0 1 @@ -244,6 +252,7 @@ 0 1 BFM + Differential None None None @@ -311,6 +320,7 @@ 1 DM_NO_DBI 64 + false false false 10000 @@ -360,12 +370,14 @@ false Disable false + false true SIMPLE_TG OFF false 1 false + false 1 false 1 @@ -393,19 +405,17 @@ TRUE TRUE IP_Flow - 73068 + 12 TRUE . . - 2019.1.1_AR73068 + 2021.1 OUT_OF_CONTEXT - - @@ -443,6 +453,38 @@ + + + diff --git a/top/x400/ip/eth_100g_bd/Makefile.inc b/top/x400/ip/eth_100g_bd/Makefile.inc index 8e74beb..a6197ac 100644 --- a/top/x400/ip/eth_100g_bd/Makefile.inc +++ b/top/x400/ip/eth_100g_bd/Makefile.inc @@ -21,7 +21,7 @@ sim/eth_100g_bd.v\ ip/*/ip_0/sim/*.v\ ip/*/sim/*.h\ ip/*/sim/*.v\ -ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v2_6_1/*.v\ +ip/eth_100g_bd_cmac_usplus_0_0/cmac_usplus_v3_1_4/*.v\ ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/*.v\ ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/header_files/*.h\ ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0.v\ diff --git a/top/x400/ip/eth_100g_bd/eth_100g.sv b/top/x400/ip/eth_100g_bd/eth_100g.sv index 2cd7fa5..fd9b028 100644 --- a/top/x400/ip/eth_100g_bd/eth_100g.sv +++ b/top/x400/ip/eth_100g_bd/eth_100g.sv @@ -80,6 +80,7 @@ module eth_100g #( end end + // synthesis translate_off //extra simulation checks localparam USE_MAC_CHECKS = 1; if (USE_MAC_CHECKS) begin @@ -124,6 +125,7 @@ module eth_100g #( assert (mgt_rx.TLAST == 1) else $fatal(1, "mgt_rx.TLAST must be enabled"); end + // synthesis translate_on AxiStreamIf #(.DATA_WIDTH(512),.TUSER(0),.TKEEP(0)) eth100g_tx(mgt_clk,mgt_rst); @@ -1130,23 +1132,11 @@ module eth_100g #( eth_100g_bd eth_100g_bd_i ( .refclk_clk_n(refclk_n), .refclk_clk_p(refclk_p), - .gt_rx_gt_port_0_n(rx_n[0]), - .gt_rx_gt_port_0_p(rx_p[0]), - .gt_rx_gt_port_1_n(rx_n[1]), - .gt_rx_gt_port_1_p(rx_p[1]), - .gt_rx_gt_port_2_n(rx_n[2]), - .gt_rx_gt_port_2_p(rx_p[2]), - .gt_rx_gt_port_3_n(rx_n[3]), - .gt_rx_gt_port_3_p(rx_p[3]), + .gt_serial_port_0_grx_n(rx_n), + .gt_serial_port_0_grx_p(rx_p), + .gt_serial_port_0_gtx_n(tx_n), + .gt_serial_port_0_gtx_p(tx_p), .init_clk(clk100), - .gt_tx_gt_port_0_n(tx_n[0]), - .gt_tx_gt_port_0_p(tx_p[0]), - .gt_tx_gt_port_1_n(tx_n[1]), - .gt_tx_gt_port_1_p(tx_p[1]), - .gt_tx_gt_port_2_n(tx_n[2]), - .gt_tx_gt_port_2_p(tx_p[2]), - .gt_tx_gt_port_3_n(tx_n[3]), - .gt_tx_gt_port_3_p(tx_p[3]), .sys_reset(areset), .usr_rx_reset(usr_rx_reset), .usr_tx_reset(usr_tx_reset), diff --git a/top/x400/ip/eth_100g_bd/eth_100g_bd.tcl b/top/x400/ip/eth_100g_bd/eth_100g_bd.tcl index 624e090..161597f 100644 --- a/top/x400/ip/eth_100g_bd/eth_100g_bd.tcl +++ b/top/x400/ip/eth_100g_bd/eth_100g_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -76,10 +76,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -100,19 +100,19 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -123,12 +123,12 @@ set bCheckIPsPassed 1 set bCheckIPs 1 if { $bCheckIPs == 1 } { set list_check_ips "\ -xilinx.com:ip:cmac_usplus:2.6\ +xilinx.com:ip:cmac_usplus:3.1\ xilinx.com:ip:xlconstant:1.1\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -138,14 +138,14 @@ xilinx.com:ip:xlconstant:1.1\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -169,14 +169,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -194,9 +194,7 @@ proc create_root_design { parentCell } { set eth100g_tx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_tx ] - set gt_rx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_rx ] - - set gt_tx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:gt_ports:2.0 gt_tx ] + set gt_serial_port_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_serial_port_0 ] set refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 refclk ] set_property -dict [ list \ @@ -246,10 +244,7 @@ proc create_root_design { parentCell } { ] $gt_txusrclk2 set init_clk [ create_bd_port -dir I -type clk init_clk ] set pm_tick [ create_bd_port -dir I pm_tick ] - set rx_clk [ create_bd_port -dir I -type clk rx_clk ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {322265625} \ - ] $rx_clk + set rx_clk [ create_bd_port -dir I -type clk -freq_hz 322265625 rx_clk ] set s_axi_aclk [ create_bd_port -dir I -type clk s_axi_aclk ] set s_axi_sreset [ create_bd_port -dir I -type rst s_axi_sreset ] set_property -dict [ list \ @@ -267,7 +262,7 @@ proc create_root_design { parentCell } { set usr_tx_reset [ create_bd_port -dir O -type rst usr_tx_reset ] # Create instance: cmac_usplus_0, and set properties - set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:2.6 cmac_usplus_0 ] + set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_0 ] set_property -dict [ list \ CONFIG.CMAC_CAUI4_MODE {1} \ CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \ @@ -289,7 +284,7 @@ proc create_root_design { parentCell } { CONFIG.LANE7_GT_LOC {NA} \ CONFIG.LANE8_GT_LOC {NA} \ CONFIG.LANE9_GT_LOC {NA} \ - CONFIG.NUM_LANES {4} \ + CONFIG.NUM_LANES {4x25} \ CONFIG.RX_CHECK_ACK {0} \ CONFIG.RX_EQ_MODE {AUTO} \ CONFIG.RX_FLOW_CONTROL {1} \ @@ -312,8 +307,7 @@ proc create_root_design { parentCell } { # Create interface connections connect_bd_intf_net -intf_net RefClk_1 [get_bd_intf_ports refclk] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk] - connect_bd_intf_net -intf_net Rx_1 [get_bd_intf_ports gt_rx] [get_bd_intf_pins cmac_usplus_0/gt_rx] - connect_bd_intf_net -intf_net cmac_usplus_0_gt_tx [get_bd_intf_ports gt_tx] [get_bd_intf_pins cmac_usplus_0/gt_tx] + connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_ports gt_serial_port_0] [get_bd_intf_pins cmac_usplus_0/gt_serial_port] connect_bd_intf_net -intf_net cmac_usplus_0_lbus_rx [get_bd_intf_ports eth100g_rx] [get_bd_intf_pins cmac_usplus_0/lbus_rx] connect_bd_intf_net -intf_net eth_100g_tx_1 [get_bd_intf_ports eth100g_tx] [get_bd_intf_pins cmac_usplus_0/lbus_tx] connect_bd_intf_net -intf_net sDrp_1 [get_bd_intf_ports core_drp] [get_bd_intf_pins cmac_usplus_0/core_drp] @@ -340,7 +334,7 @@ proc create_root_design { parentCell } { connect_bd_net -net tie_zero_dout [get_bd_pins cmac_usplus_0/gtwiz_reset_rx_datapath] [get_bd_pins cmac_usplus_0/gtwiz_reset_tx_datapath] [get_bd_pins tie_zero/dout] # Create address segments - create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] SEG_cmac_usplus_0_Reg + assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] -force # Restore current instance diff --git a/top/x400/ip/eth_100g_bd/lbus_tb/Makefile b/top/x400/ip/eth_100g_bd/lbus_tb/Makefile index 3c57e74..49c6f68 100644 --- a/top/x400/ip/eth_100g_bd/lbus_tb/Makefile +++ b/top/x400/ip/eth_100g_bd/lbus_tb/Makefile @@ -35,7 +35,7 @@ $(AXI4S_SV_SRCS) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4 +MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_5 MODELSIM_ARGS += glbl -t 1fs # Define toplevel module TB_TOP_MODULE ?= lbus_all_tb @@ -50,8 +50,8 @@ $(VIVADO_PATH)/data/verilog/src/glbl.v \ # Suppressing the following worthless reminder. #* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] - # Extra checking for conflicts with always_comb and always_latch variables is done at vopt time -SVLOG_ARGS = -suppress 2583 -keep_delta -VLOG_ARGS = -keep_delta +SVLOG_ARGS = -suppress 2583 -keep_delta +VLOG_ARGS = -keep_delta #------------------------------------------------- # Bottom-of-Makefile diff --git a/top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci b/top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci index 8888402..5c52fdf 100644 --- a/top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci +++ b/top/x400/ip/fifo_4k_2clk/fifo_4k_2clk.xci @@ -13,13 +13,15 @@ 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 1 0 0 @@ -43,7 +45,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -59,7 +61,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -68,12 +70,14 @@ 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 1 0 @@ -98,7 +102,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -114,7 +118,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -123,8 +127,9 @@ 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -509,12 +514,12 @@ TRUE TRUE IP_Flow - 4 + 5 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -569,6 +574,14 @@ + + + diff --git a/top/x400/ip/fifo_short_2clk/fifo_short_2clk.xci b/top/x400/ip/fifo_short_2clk/fifo_short_2clk.xci index cc0f896..249357e 100644 --- a/top/x400/ip/fifo_short_2clk/fifo_short_2clk.xci +++ b/top/x400/ip/fifo_short_2clk/fifo_short_2clk.xci @@ -13,13 +13,15 @@ 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 1 0 0 @@ -43,7 +45,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -59,7 +61,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -68,12 +70,14 @@ 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 1 0 @@ -98,7 +102,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -114,7 +118,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -123,8 +127,9 @@ 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -509,12 +514,12 @@ TRUE TRUE IP_Flow - 4 + 5 TRUE . . - 2019.1 + 2021.1 OUT_OF_CONTEXT @@ -571,6 +576,14 @@ + + + diff --git a/top/x400/ip/hb47_1to2/hb47_1to2.xci b/top/x400/ip/hb47_1to2/hb47_1to2.xci index 7959aa2..6b0eccc 100644 --- a/top/x400/ip/hb47_1to2/hb47_1to2.xci +++ b/top/x400/ip/hb47_1to2/hb47_1to2.xci @@ -9,11 +9,11 @@ hb47_1to2 - ACTIVE_LOW 100000000 + 0 0 - 0.000 + 0.0 0 1 1 @@ -30,7 +30,7 @@ 0 0 undef - 0.000 + 0.0 12 0 0 @@ -43,7 +43,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -56,7 +56,7 @@ 0 0 undef - 0.000 + 0.0 4 0 0 @@ -69,7 +69,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -151,6 +151,7 @@ Vector -62, 0, 194, 0, -440, 0, 855, 0, -1505, 0, 2478, 0, -3900, 0, 5990, 0, -9187, 0, 14632, 0, -26536, 0, 83009, 131071, 83009, 0, -26536, 0, 14632, 0, -9187, 0, 5990, 0, -3900, 0, 2478, 0, -1505, 0, 855, 0, -440, 0, 194, 0, -62 Automatic + false no_coe_file_loaded 0 false @@ -160,13 +161,20 @@ 18 24 hb47_1to2 + false + false + false + false Not_Required 1 Automatic 0 + false + false Signed 16 1 + false false Systolic_Multiply_Accumulate 1 @@ -184,18 +192,23 @@ false Not_Required Automatic + false + false 1 1 2 + false Area None None + false Automatic Convergent_Rounding_to_Even 18 0.5 0.0 P4-0,P4-1,P4-2,P4-3,P4-4 + false Automatic Integer_Coefficients Output_Sample_Period @@ -226,12 +239,12 @@ TRUE TRUE IP_Flow - 12 + 16 TRUE . . - 2019.1.1_AR73068 + 2021.1 OUT_OF_CONTEXT @@ -291,6 +304,24 @@ + + + diff --git a/top/x400/ip/hb47_2to1/hb47_2to1.xci b/top/x400/ip/hb47_2to1/hb47_2to1.xci index e9af188..2e19e0c 100644 --- a/top/x400/ip/hb47_2to1/hb47_2to1.xci +++ b/top/x400/ip/hb47_2to1/hb47_2to1.xci @@ -9,11 +9,11 @@ hb47_2to1 - ACTIVE_LOW 100000000 + 0 0 - 0.000 + 0.0 0 1 1 @@ -30,7 +30,7 @@ 0 0 undef - 0.000 + 0.0 6 0 0 @@ -43,7 +43,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -56,7 +56,7 @@ 0 0 undef - 0.000 + 0.0 8 0 0 @@ -69,7 +69,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -78,7 +78,7 @@ 35,35,35,35 fixed hb47_2to1.mif - 47 + 24 2 0 0,0,0,0 @@ -86,7 +86,7 @@ 18,18,18,18 0 18 - 47 + 24 1 4 hb47_2to1 @@ -115,15 +115,15 @@ 1 1 2 - 52 - 2 + 30 + 1 0 0 48 1 1 1 - 47 + 24 1 47 0 @@ -137,7 +137,7 @@ 2,3,2,3 1 4 - 0 + 1 0 0 64 @@ -151,22 +151,30 @@ Vector -62 0 194 0 -440 0 855 0 -1505 0 2478 0 -3900 0 5990 0 -9187 0 14632 0 -26536 0 83009 131071 83009 0 -26536 0 14632 0 -9187 0 5990 0 -3900 0 2478 0 -1505 0 855 0 -440 0 194 0 -62 Automatic - hb47.coe + false + no_coe_file_loaded 0 false 1 Signed Inferred 18 - 47 + 24 hb47_2to1 + false + false + false + false Not_Required 1 Automatic 0 + false + false Signed 16 2 + false false Systolic_Multiply_Accumulate 1 @@ -184,18 +192,23 @@ false Not_Required Automatic + false + false 1 1 2 + false Area None None + false Automatic Convergent_Rounding_to_Even 17 0.4 0.0 P4-0,P4-1,P4-2,P4-3,P4-4 + false Automatic Integer_Coefficients Input_Sample_Period @@ -226,12 +239,12 @@ TRUE TRUE IP_Flow - 12 + 16 TRUE . . - 2019.1.1_AR73068 + 2021.1 OUT_OF_CONTEXT @@ -306,6 +319,24 @@ + + + diff --git a/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl b/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl index 49ced97..9ffe461 100644 --- a/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl +++ b/top/x400/ip/x4xx_ps_rfdc_bd/x4xx_ps_rfdc_bd.tcl @@ -20,12 +20,12 @@ set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ -set scripts_vivado_version 2019.1 +set scripts_vivado_version 2021.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } @@ -83,10 +83,10 @@ if { ${design_name} eq "" } { # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: @@ -107,11 +107,11 @@ if { ${design_name} eq "" } { # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } @@ -123,10 +123,10 @@ if { ${design_name} eq "" } { [15:8] = invert DAC channels [7:0] = invert ADC channels" [get_bd_designs $design_name] -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." +common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg} return $nRet } @@ -143,16 +143,16 @@ xilinx.com:ip:xlconcat:2.1\ xilinx.com:ip:xlconstant:1.1\ xilinx.com:ip:clk_wiz:6.0\ xilinx.com:ip:axi_gpio:2.0\ -xilinx.com:ip:usp_rf_data_converter:2.1\ +xilinx.com:ip:usp_rf_data_converter:2.5\ xilinx.com:ip:xlslice:1.0\ xilinx.com:ip:axi_protocol_converter:2.1\ xilinx.com:ip:axi_dma:7.1\ xilinx.com:ip:smartconnect:1.0\ -xilinx.com:ip:util_ds_buf:2.1\ +xilinx.com:ip:util_ds_buf:2.2\ " set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." foreach ip_vlnv $list_check_ips { set ip_obj [get_ipdefs -all $ip_vlnv] @@ -162,7 +162,7 @@ xilinx.com:ip:util_ds_buf:2.1\ } if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } set bCheckIPsPassed 0 } @@ -182,7 +182,7 @@ gpio_to_axis_mux\ " set list_mods_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." + common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ." foreach mod_vlnv $list_check_mods { if { [can_resolve_reference $mod_vlnv] == 0 } { @@ -191,14 +191,14 @@ gpio_to_axis_mux\ } if { $list_mods_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } - common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above." + catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" } + common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above." set bCheckIPsPassed 0 } } if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." return 3 } @@ -213,21 +213,21 @@ proc create_hier_cell_rf_clock_buffers { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -252,13 +252,13 @@ proc create_hier_cell_rf_clock_buffers { parentCell nameHier } { create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll # Create instance: rfdc_clk_1x_buf, and set properties - set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_1x_buf ] + set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_1x_buf ] set_property -dict [ list \ CONFIG.C_BUF_TYPE {BUFGCE} \ ] $rfdc_clk_1x_buf # Create instance: rfdc_clk_2x_buf, and set properties - set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 rfdc_clk_2x_buf ] + set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_2x_buf ] set_property -dict [ list \ CONFIG.C_BUF_TYPE {BUFGCE} \ ] $rfdc_clk_2x_buf @@ -281,21 +281,21 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_calibration_muxes() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -347,10 +347,10 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } { set block_name gpio_to_axis_mux set block_cell_name gpio_to_axis_mux_0 if { [catch {set gpio_to_axis_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $gpio_to_axis_mux_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } set_property -dict [ list \ @@ -385,21 +385,21 @@ proc create_hier_cell_ThresholdRegister { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ThresholdRegister() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -475,21 +475,21 @@ proc create_hier_cell_eth_dma_internal { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_eth_dma_internal() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -577,21 +577,21 @@ proc create_hier_cell_axi_interconnect_common { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_axi_interconnect_common() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -666,21 +666,21 @@ proc create_hier_cell_rfdc { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rfdc() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -800,10 +800,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } { set block_name capture_sysref set block_cell_name capture_sysref if { [catch {set capture_sysref [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $capture_sysref eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -823,10 +823,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } { set block_name clock_gates set block_cell_name clock_gates_0 if { [catch {set clock_gates_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $clock_gates_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -941,7 +941,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } { create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers # Create instance: rf_data_converter, and set properties - set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.1 rf_data_converter ] + set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ] set_property -dict [ list \ CONFIG.ADC0_Enable {1} \ CONFIG.ADC0_Fabric_Freq {184.320} \ @@ -1200,10 +1200,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } { set block_name rf_nco_reset set block_cell_name rf_nco_reset_0 if { [catch {set rf_nco_reset_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $rf_nco_reset_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -1211,10 +1211,10 @@ proc create_hier_cell_rfdc { parentCell nameHier } { set block_name rf_reset_controller set block_cell_name rf_reset_controller_0 if { [catch {set rf_reset_controller_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { - catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } elseif { $rf_reset_controller_0 eq "" } { - catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} return 1 } @@ -1354,21 +1354,21 @@ proc create_hier_cell_ps { parentCell nameHier } { variable script_folder if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_ps() - Empty argument(s)!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_ps() - Empty argument(s)!"} return } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -1441,6 +1441,11 @@ proc create_hier_cell_ps { parentCell nameHier } { # Create instance: cpld_jtag_engine, and set properties set cpld_jtag_engine [ create_bd_cell -type ip -vlnv ettus.com:ip:axi_bitq:1.0 cpld_jtag_engine ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {40000000} \ + CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \ + ] [get_bd_intf_pins /ps/cpld_jtag_engine/S_AXI] + set_property -dict [ list \ CONFIG.FREQ_HZ {40000000} \ CONFIG.CLK_DOMAIN {x4xx_ps_rfdc_bd_clk40} \ @@ -1951,8 +1956,14 @@ proc create_hier_cell_ps { parentCell nameHier } { CONFIG.PSU_MIO_9_POLARITY {Default} \ CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ CONFIG.PSU_MIO_9_SLEW {slow} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART 1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ - CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {GPIO0 MIO#GPIO0 MIO#I2C 0#I2C 0#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#SPI 1#SPI\ +1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO0\ +MIO#GPIO0 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#UART 0#UART 0#UART 1#UART\ +1#PMU GPO 2#PMU GPO 3#I2C 1#I2C 1#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1\ +MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB\ +0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem\ +3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3}\ + CONFIG.PSU_MIO_TREE_SIGNALS {gpio0[0]#gpio0[1]#scl_out#sda_out#gpio0[4]#gpio0[5]#sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#sdio0_data_out[4]#sdio0_data_out[5]#sdio0_data_out[6]#sdio0_data_out[7]#sdio0_cmd_out#sdio0_clk_out#sdio0_bus_pow#gpio0[24]#gpio0[25]#gpio1[26]#gpio1[27]#gpio1[28]#gpio1[29]#rxd#txd#txd#rxd#gpo[2]#gpo[3]#scl_out#sda_out#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\ CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {8} \ @@ -2664,6 +2675,7 @@ proc create_hier_cell_ps { parentCell nameHier } { CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ @@ -2771,14 +2783,37 @@ proc create_hier_cell_ps { parentCell nameHier } { CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ CONFIG.PSU__PROTECTION__DEBUG {0} \ CONFIG.PSU__PROTECTION__ENABLE {0} \ - CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD000000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD020000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD040000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware | SA:0xFD610000\ +;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware | SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware}\ CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ - CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ - CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ - CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB\ +;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB\ +;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000\ +;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU\ +Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure\ +;WrAllowed:Read/Write;subsystemId:PMU Firmware}\ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\ CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ - CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\ +Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\ CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \ CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ @@ -3046,14 +3081,14 @@ proc create_root_design { parentCell } { # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } @@ -3411,18 +3446,16 @@ proc create_root_design { parentCell } { CONFIG.POLARITY {ACTIVE_HIGH} \ ] $adc_reset_pulse_dclk set adc_rfdc_axi_resetn_rclk [ create_bd_port -dir O adc_rfdc_axi_resetn_rclk ] - set bus_clk [ create_bd_port -dir I -type clk bus_clk ] + set bus_clk [ create_bd_port -dir I -type clk -freq_hz 200000000 bus_clk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {m_axis_eth_dma:s_axis_eth_dma:s_axi_hpc1} \ CONFIG.ASSOCIATED_RESET {bus_rstn} \ - CONFIG.FREQ_HZ {200000000} \ ] $bus_clk set bus_rstn [ create_bd_port -dir I -type rst bus_rstn ] - set clk40 [ create_bd_port -dir I -type clk clk40 ] + set clk40 [ create_bd_port -dir I -type clk -freq_hz 40000000 clk40 ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {m_axi_app:m_axi_mpm_ep:m_axi_core:m_axi_rpu:m_axi_eth_internal} \ CONFIG.ASSOCIATED_RESET {clk40_rstn} \ - CONFIG.FREQ_HZ {40000000} \ ] $clk40 set clk40_rstn [ create_bd_port -dir I -type rst clk40_rstn ] set dac_data_in_resetn_dclk [ create_bd_port -dir O dac_data_in_resetn_dclk ] @@ -3473,10 +3506,7 @@ proc create_root_design { parentCell } { set pl_resetn1 [ create_bd_port -dir O -type rst pl_resetn1 ] set pl_resetn2 [ create_bd_port -dir O -type rst pl_resetn2 ] set pl_resetn3 [ create_bd_port -dir O -type rst pl_resetn3 ] - set pll_ref_clk_in [ create_bd_port -dir I -type clk pll_ref_clk_in ] - set_property -dict [ list \ - CONFIG.FREQ_HZ {61440000} \ - ] $pll_ref_clk_in + set pll_ref_clk_in [ create_bd_port -dir I -type clk -freq_hz 61440000 pll_ref_clk_in ] set pll_ref_clk_out [ create_bd_port -dir O -type clk pll_ref_clk_out ] set_property -dict [ list \ CONFIG.FREQ_HZ {61440000} \ @@ -3494,16 +3524,14 @@ proc create_root_design { parentCell } { CONFIG.FREQ_HZ {368640000} \ ] $rfdc_clk_2x set rfdc_irq [ create_bd_port -dir O -type intr rfdc_irq ] - set s_axi_hp0_aclk [ create_bd_port -dir I -type clk s_axi_hp0_aclk ] + set s_axi_hp0_aclk [ create_bd_port -dir I -type clk -freq_hz 40000000 s_axi_hp0_aclk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {s_axi_hp0} \ CONFIG.ASSOCIATED_RESET {s_axi_hp0_aresetn} \ - CONFIG.FREQ_HZ {40000000} \ ] $s_axi_hp0_aclk - set s_axi_hp1_aclk [ create_bd_port -dir I -type clk s_axi_hp1_aclk ] + set s_axi_hp1_aclk [ create_bd_port -dir I -type clk -freq_hz 40000000 s_axi_hp1_aclk ] set_property -dict [ list \ CONFIG.ASSOCIATED_BUSIF {s_axi_hp1} \ - CONFIG.FREQ_HZ {40000000} \ ] $s_axi_hp1_aclk set s_axi_hpc0_aclk [ create_bd_port -dir I -type clk s_axi_hpc0_aclk ] set_property -dict [ list \ @@ -3616,51 +3644,45 @@ proc create_root_design { parentCell } { connect_bd_net -net sysref_pl_in_1 [get_bd_ports sysref_pl_in] [get_bd_pins rfdc/sysref_pl_in] # Create address segments - create_bd_addr_seg -range 0x00004000 -offset 0x0010000A4000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] SEG_axi_eth_dma_internal_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000155000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000154000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] SEG_axi_gpio_data_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] SEG_cpld_jtag_engine_reg0 - create_bd_addr_seg -range 0x00010000 -offset 0x001000140000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] SEG_data_clock_mmcm_Reg - create_bd_addr_seg -range 0x000200000000 -offset 0x001200000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] SEG_m_axi_app_Reg - create_bd_addr_seg -range 0x00004000 -offset 0x0010000A0000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_core/Reg] SEG_m_axi_core_0_Reg - create_bd_addr_seg -range 0x00004000 -offset 0x0010000A8000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] SEG_m_axi_eth_internal_Reg - create_bd_addr_seg -range 0x00020000 -offset 0x001000080000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] SEG_m_axi_mpm_ep_Reg - create_bd_addr_seg -range 0x00010000 -offset 0x80000000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] SEG_m_axi_rpu_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000156000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] SEG_reg_clock_gate_control_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000150000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] SEG_reg_invert_iq_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000151000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] SEG_reg_reset_mmcm_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000153000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] SEG_reg_rf_axi_status_Reg - create_bd_addr_seg -range 0x00001000 -offset 0x001000152000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] SEG_reg_rf_reset_control_Reg - create_bd_addr_seg -range 0x00040000 -offset 0x001000100000 [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] SEG_rf_data_converter_Reg - create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH - create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH - create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW - create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_HIGH] SEG_inst_zynq_ps_HP0_DDR_HIGH - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_LOW] SEG_inst_zynq_ps_HP0_DDR_LOW - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_LPS_OCM] SEG_inst_zynq_ps_HP0_LPS_OCM - create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_HIGH] SEG_inst_zynq_ps_HP1_DDR_HIGH - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_LOW] SEG_inst_zynq_ps_HP1_DDR_LOW - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_LPS_OCM] SEG_inst_zynq_ps_HP1_LPS_OCM - create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_HIGH] SEG_inst_zynq_ps_HPC0_DDR_HIGH - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_LOW] SEG_inst_zynq_ps_HPC0_DDR_LOW - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_LPS_OCM] SEG_inst_zynq_ps_HPC0_LPS_OCM - create_bd_addr_seg -range 0x000800000000 -offset 0x000800000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] SEG_inst_zynq_ps_HPC1_DDR_HIGH - create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] SEG_inst_zynq_ps_HPC1_DDR_LOW - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM + assign_bd_address -offset 0x0010000A4000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] -force + assign_bd_address -offset 0x001000155000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] -force + assign_bd_address -offset 0x001000154000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] -force + assign_bd_address -offset 0x001000000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] -force + assign_bd_address -offset 0x001000140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] -force + assign_bd_address -offset 0x001200000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] -force + assign_bd_address -offset 0x0010000A0000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_core/Reg] -force + assign_bd_address -offset 0x0010000A8000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_eth_internal/Reg] -force + assign_bd_address -offset 0x001000080000 -range 0x00020000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_mpm_ep/Reg] -force + assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_rpu/Reg] -force + assign_bd_address -offset 0x001000156000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_clock_gate_control/S_AXI/Reg] -force + assign_bd_address -offset 0x001000150000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_invert_iq/S_AXI/Reg] -force + assign_bd_address -offset 0x001000151000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_reset_mmcm/S_AXI/Reg] -force + assign_bd_address -offset 0x001000153000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_axi_status/S_AXI/Reg] -force + assign_bd_address -offset 0x001000152000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control/S_AXI/Reg] -force + assign_bd_address -offset 0x001000100000 -range 0x00040000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] -force + assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force + assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force + assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force + assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_HIGH] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_DDR_LOW] -force + assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hp0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP2/HP0_LPS_OCM] -force + assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_HIGH] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_DDR_LOW] -force + assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hp1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP3/HP1_LPS_OCM] -force + assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_HIGH] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_DDR_LOW] -force + assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hpc0] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP0/HPC0_LPS_OCM] -force + assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force + assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_LOW] -force + assign_bd_address -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces s_axi_hpc1] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] -force # Exclude Address Segments - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S/SEG_inst_zynq_ps_HPC1_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM/SEG_inst_zynq_ps_HPC1_LPS_OCM] - - create_bd_addr_seg -range 0x01000000 -offset 0xFF000000 [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] SEG_inst_zynq_ps_HPC1_LPS_OCM - exclude_bd_addr_seg [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/Data_SG/SEG_inst_zynq_ps_HPC1_LPS_OCM] - + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_S2MM] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] + exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_LPS_OCM] # Restore current instance diff --git a/top/x400/ip/xge_pcs_pma/Makefile.inc b/top/x400/ip/xge_pcs_pma/Makefile.inc index 0d30a55..0f95d07 100644 --- a/top/x400/ip/xge_pcs_pma/Makefile.inc +++ b/top/x400/ip/xge_pcs_pma/Makefile.inc @@ -14,10 +14,10 @@ $(IP_XGE_PCS_PMA_EXAMPLE_SRCS) IP_XGE_PCS_PMA_HDL_SIM_SRCS = $(IP_DIR)/xge_pcs_pma/model_10gbe.sv \ $(wildcard $(addprefix $(IP_BUILD_DIR)/xge_pcs_pma/, \ xge_pcs_pma.v \ -hdl/xxv_ethernet_v3_0_vl_rfs.sv \ +hdl/xxv_ethernet_v4_0_vl_rfs.sv \ ip_0/hdl/*.v \ ip_0/sim/*.v \ -xxv_ethernet_v3_0_1/*.v \ +xxv_ethernet_v4_0_0/*.v \ )) IP_XGE_PCS_PMA_EXAMPLE_SRCS = \ @@ -25,13 +25,7 @@ $(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_common_wrapper.v \ $(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/xge_pcs_pma_gt_gtye4_common_wrapper.v \ $(IP_BUILD_DIR)/xge_pcs_pma_ex/imports/gtwizard_ultrascale_v1_7_gtye4_common.v \ -# Describe the paths for the patch file, the file to be patched, and the -# patched copy of the file. -IP_XGE_FILE_PATCH = $(IP_DIR)/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch -IP_XGE_FILE_TO_PATCH = $(IP_BUILD_DIR)/xge_pcs_pma/xxv_ethernet_v3_0_1/xge_pcs_pma_wrapper.v -IP_XGE_PATCHED_FILE = $(IP_BUILD_DIR)/xge_pcs_pma_wrapper.v.patched - -IP_XGE_PCS_PMA_SRCS = $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_PATCHED_FILE) +IP_XGE_PCS_PMA_SRCS = $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_BUILD_DIR)/xge_pcs_pma/xxv_ethernet_v4_0_0/xge_pcs_pma_wrapper.v IP_XGE_PCS_PMA_OUTS = \ $(IP_BUILD_DIR)/xge_pcs_pma/xge_pcs_pma.xci.out \ @@ -43,9 +37,5 @@ $(IP_XGE_PCS_PMA_EXAMPLE_SRCS) : $(IP_XGE_PCS_PMA_OUTS) $(IP_XGE_PCS_PMA_SRCS) $(IP_XGE_PCS_PMA_OUTS): IP_XGE_PCS_PMA_TRGT @: -IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(IP_XGE_FILE_PATCH) +IP_XGE_PCS_PMA_TRGT: $(IP_DIR)/xge_pcs_pma/xge_pcs_pma.xci $(call BUILD_VIVADO_IP,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),1) - cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_FILE_TO_PATCH).orig - cp $(IP_XGE_FILE_TO_PATCH) $(IP_XGE_PATCHED_FILE) - patch $(IP_XGE_PATCHED_FILE) $(IP_XGE_FILE_PATCH) - $(call REBUILD_VIVADO_IP_WITH_PATCH,xge_pcs_pma,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0,$(call RESOLVE_PATH,$(IP_XGE_PATCHED_FILE)),$(call RESOLVE_PATH,$(IP_XGE_FILE_TO_PATCH))) diff --git a/top/x400/ip/xge_pcs_pma/ten_gige_phy.v b/top/x400/ip/xge_pcs_pma/ten_gige_phy.v index b419c45..e3df97b 100644 --- a/top/x400/ip/xge_pcs_pma/ten_gige_phy.v +++ b/top/x400/ip/xge_pcs_pma/ten_gige_phy.v @@ -55,11 +55,10 @@ module ten_gige_phy ( wire a_gt_reset_tx_done, gt_reset_tx_done; wire a_gt_reset_rx_done, gt_reset_rx_done; - wire stat_rx_status_tmp; - reg stat_rx_status; + wire stat_rx_status; - reg [RX_RST_COUNT_W-1:0] rst_count; - reg gt_rx_reset_in; + // reg [RX_RST_COUNT_W-1:0] rst_count; + // reg gt_rx_reset_in; //--------------------------------------------------------------------------- // Xilinx 10G/25G IP High Speed Ethernet Subsystem Instance @@ -141,7 +140,7 @@ module ten_gige_phy ( .gt_reset_rx_done_out_0 (a_gt_reset_rx_done), .gt_reset_all_in_0 (areset), .gt_tx_reset_in_0 (1'b0), - .gt_rx_reset_in_0 (gt_rx_reset_in), + .gt_rx_reset_in_0 (1'b0), .rx_reset_0 (rx_reset), .rx_mii_d_0 (xgmii_rxd), .rx_mii_c_0 (xgmii_rxc), @@ -154,7 +153,7 @@ module ten_gige_phy ( .stat_rx_local_fault_0 (), .stat_rx_block_lock_0 (), .stat_rx_valid_ctrl_code_0 (), - .stat_rx_status_0 (stat_rx_status_tmp), // rx_core_clk_0 domain + .stat_rx_status_0 (stat_rx_status), // rx_core_clk_0 domain .stat_rx_hi_ber_0 (), .stat_rx_bad_code_0 (), .stat_rx_bad_code_valid_0 (), @@ -172,7 +171,9 @@ module ten_gige_phy ( .ctl_tx_test_pattern_seed_a_0 (58'b0), .ctl_tx_test_pattern_seed_b_0 (58'b0), .ctl_tx_prbs31_test_pattern_enable_0 (1'b0), - .gt_loopback_in_0 (3'b0) + .gt_loopback_in_0 (3'b0), + .gt_txelecidle_0 (1'b0), + .gt_drprst_0 (1'b0) ); @@ -233,42 +234,4 @@ module ten_gige_phy ( .out (rx_reset) ); - // This state machine resets the RX GT part of the core periodically when - // the link is down. This is necessary due to a bug in the Xilinx IP. - always @(posedge xgmii_clk, posedge areset) begin - if (areset) begin - gt_rx_reset_in <= 0; - rst_count <= 0; - stat_rx_status <= 0; - end else begin - stat_rx_status <= stat_rx_status_tmp; - - // Periodically reset until link is up - if (!stat_rx_status) begin - rst_count <= rst_count + 1; - - if (!gt_rx_reset_in) begin - // We're not in reset. Wait until RX_RST_WAIT cycles have elapsed, - // then reset. - if (rst_count == RX_RST_WAIT-1) begin - rst_count <= 0; - gt_rx_reset_in <= 1; - end - end else begin - // We're in reset. Wait until RX_RST_DURATION cycles have elapsed - // before deasserting reset. - if (rst_count == RX_RST_DURATION-1) begin - rst_count <= 0; - gt_rx_reset_in <= 0; - end - end - - // Currently linked, so all is well - end else begin - rst_count <= 0; - gt_rx_reset_in <= 0; - end - end - end - endmodule diff --git a/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci b/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci index aeda24d..170fdff 100644 --- a/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci +++ b/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci @@ -7,24 +7,28 @@ xge_pcs_pma - + 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -37,7 +41,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -50,7 +54,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -63,7 +67,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -76,7 +80,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -89,7 +93,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -102,7 +106,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -115,7 +119,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -128,7 +132,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -141,7 +145,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -154,7 +158,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -167,7 +171,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -180,7 +184,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -193,7 +197,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -206,7 +210,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -219,7 +223,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -232,7 +236,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -245,7 +249,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -258,7 +262,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -271,7 +275,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -284,7 +288,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -297,7 +301,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -310,7 +314,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -323,7 +327,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -336,7 +340,7 @@ 0 0 undef - 0.000 + 0.0 0 0 0 @@ -356,8 +360,9 @@ 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -370,26 +375,30 @@ 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 0 0 @@ -397,8 +406,9 @@ + 0 0 - 0.000 + 0.0 false 100000000 0 @@ -417,21 +427,25 @@ 0 0 0 + undef undef undef undef undef undef + undef undef undef undef undef undef + undef undef undef undef undef undef + undef undef undef undef @@ -442,21 +456,25 @@ 0 0 0 + undef undef undef undef undef undef + undef undef undef undef undef undef + undef undef undef undef undef undef + undef undef undef undef @@ -465,113 +483,142 @@ + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 + 0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 0 0 0 @@ -580,14 +627,26 @@ 0 0 0 - 156.25 + + + 156250000 undef - 156.25 + 0.0 + + + 156250000 undef - 156.25 + 0.0 + + + 156250000 undef - 156.25 + 0.0 + + + 156250000 undef + 0.0 0 0 0 @@ -616,7 +675,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -647,7 +706,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -678,7 +737,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -709,7 +768,7 @@ 1 1 1 - 0.000 + 0.0 AXI4LITE READ_WRITE 0 @@ -719,124 +778,156 @@ 0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 100000000 + 0 0 - 0.000 + 0.0 0 0 0 0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 100000000 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 0 0 0 0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 + 0 0 - 0.000 + 0.0 0 0 0 @@ -855,9 +946,11 @@ 7 BASE-R Asynchronous + CMACE4_X0Y0 Ethernet PCS/PMA 64-bit MII 0 + 0 1 0 0 @@ -867,6 +960,7 @@ 0 zynquplus 0 + NA 4 100.00 Quad X0Y0 @@ -881,7 +975,7 @@ 0 0 0 - 10 + 30 X0Y16 NA NA @@ -896,19 +990,23 @@ AUTO 0 0 + 4000 0 4 1 0 + 0 1 100 BASE-R Asynchronous + CMACE4_X0Y0 Ethernet PCS/PMA 64-bit xge_pcs_pma MII Custom 0 + 0 1 0 0 @@ -918,6 +1016,7 @@ 0 Custom 0 + NA 100.00 Quad_X0Y4 1 @@ -962,12 +1061,12 @@ TRUE TRUE IP_Flow - 1 + 0 TRUE . . - 2019.1.1 + 2021.1 OUT_OF_CONTEXT @@ -1177,6 +1276,73 @@ + + + diff --git a/top/x400/ip/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch b/top/x400/ip/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch deleted file mode 100644 index ba059bc..0000000 --- a/top/x400/ip/xge_pcs_pma/xge_pcs_pma_wrapper.v.patch +++ /dev/null @@ -1,30 +0,0 @@ -692a693,712 -> -> //--------------------------------------------------------------------------- -> // Workaround for link status bug. See SR 10471238 for details. -> //--------------------------------------------------------------------------- -> -> reg [13:0] rx_clk_noctrlcode_count; -> -> always @(posedge rx_core_clk_0) begin -> if (rx_reset_done_0 == 1'b1) begin -> rx_clk_noctrlcode_count <= 14'h270F; -> end else begin -> if (stat_rx_valid_ctrl_code_0 == 1'b1) begin -> rx_clk_noctrlcode_count <= 14'h270F; -> end else begin -> rx_clk_noctrlcode_count <= rx_clk_noctrlcode_count - 1; -> end -> end -> end -> -> //--------------------------------------------------------------------------- -700c720,725 -< if(stat_rx_block_lock_0 == 1'b0) ---- -> //------------------------------------------------------------------------ -> // Workaround for link status bug. See SR 10471238 for details. -> // Original code: if(stat_rx_block_lock_0 == 1'b0) -> // New code: -> if(stat_rx_block_lock_0 == 1'b0 || rx_clk_noctrlcode_count ==14'h0) -> //------------------------------------------------------------------------ diff --git a/top/x400/setupenv.sh b/top/x400/setupenv.sh index 80da944..3c6420d 100644 --- a/top/x400/setupenv.sh +++ b/top/x400/setupenv.sh @@ -5,8 +5,8 @@ # SPDX-License-Identifier: LGPL-3.0-or-later # -VIVADO_VER=2019.1 -VIVADO_VER_FULL=2019.1.1_AR73068 +VIVADO_VER=2021.1 +VIVADO_VER_FULL=2021.1 DISPLAY_NAME="USRP-X4xx" REPO_BASE_PATH=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) diff --git a/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv b/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv index 96c2cf8..c2639eb 100644 --- a/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv +++ b/top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv @@ -579,7 +579,7 @@ module x4xx_qsfp_wrapper_tb #( end repeat (4) axi.rd(LANE_BASE+REG_MAC_LSB,data); - if (MGT_PROTOCOL == `MGT_100GbE && !USE_MAC) begin + if ((MGT_PROTOCOL == `MGT_100GbE && !USE_MAC) || (MGT_PROTOCOL == `MGT_10GbE && USE_MAC)) begin reg_link_up = 1; end @@ -592,7 +592,8 @@ module x4xx_qsfp_wrapper_tb #( else axi.rd(LANE_BASE+REG_MAC_CTRL_STATUS,32'h0000_0080); else assert(1); - axi.rd(LANE_BASE+REG_PHY_CTRL_STATUS,0); + + axi.rd(LANE_BASE+REG_PHY_CTRL_STATUS,(MGT_PROTOCOL == `MGT_10GbE && USE_MAC) ? reg_link_up : 0); // en 0 / value 1 axi.rd(LANE_BASE+REG_MAC_LED_CTL,0); // enabled with value 0