miegl/b210-k7-fpga
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Sam O'Brien c41bd8f72b fpga: e320: Upgrade to Vivado 2021.1 
Original-commit: 1f57d67c4ceadbb19ce203ee9ad9e46f612c0a76
2022-08-25 13:55:30 -05:00
export/x300/radio
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
lib
fpga: lib: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
sim
fpga: Fix first arg in calls to $fatal()
2022-06-28 10:34:18 -05:00
tools
fpga: tools: Fix HLS IP builder for Vivado 2021.1
2022-08-25 13:55:30 -05:00
top
fpga: e320: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
LICENSE.md
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
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84 MiB
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Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%