This commit refactors the X410's CPLDs build process to make it similar to other
FPGA targets within the repo. The new process relies on basic Quartus build
utilities.
Additionally, this commit adds support for an alternative MAX10 CPLD for the
motherboard CPLD implementation. Both previous (10M04) and new variant
(10M08) are supported concurrently. The images package mapping is updated to
reflect these changes.
Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.
Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
Reconnect the signals from the White Rabbit module to the TDC in the
FPGA.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c0637bae1e4a0ddb996cf2b7eadfad22f782874b
White Rabbit is not supported in X410, however the register map included an
incorrect reference to this unsupported feature.
This commit removes the WR reference from both the source and html files.
Original-commit: 7edd92dbcf2da1a1c0fabe02a97fdb6afdc89077
Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.
Original-commit: b0033158a4c520063540881451d8daac91e98714
Change version from a numeric to a string, in order to
differentiate between versions like "1.1" and "1.10".
Original-commit: ca21048bd2f832b20bb36763f76d46b861b697a5
This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This
makes the naming consistent with the rest of the build process (which
uses "e310" for all variants of e31x) and fixes an issue in which the
wrong file name was used by rfnoc_image_builder.
Original-commit: bbd43b16e18ef0a0311ddf4635cbd29c4ac3c367
The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 413ebee61254fd0b9ab0cd11b475b8a849579cd8
Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.
Signed-off-by: mattprost <matt.prost@ni.com>
Original-commit: 437381bd2cfe137c5e7e2a70aab8226bfb1c70cd
This updates the IO signatures so that all devices and RFNoC blocks use
the same IO signature for the DRAM. This is needed because the IO
signatures must match between the RFNoC blocks and the devices. This
means that some devices have extra bits in the IO signature for the
address, but the extra bits will simply be ignored.
Original-commit: 8f09caaa06725d2364c63ac7cff02f3298895f4a
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: 9c4a23f0a2a2d38ace75e4ab29f6f62f64155d81
This implements the same change that was made for E31x. The same issue
wasn't reproduced on N3xx, however this change keeps the code
consistent and eliminates the potential for the same problem.
Original-commit: e94a209c5b2559348593a6732d694fd49ab59ad0
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.
Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67
It was set to E320_HG, which is not a valid target, causing build errors
unless -t E320_1G was provided to rfnoc_image_builder.
Original-commit: 9ed42affcaa88e026cb4f82807e69b546ed30c8c
Device was set to e31x, but this is not a valid device type. All e31x
devices use the e310 device type.
Original-commit: 60b76ebb31f9d1672c1b18367346b3fb522e13e9
This increases the size of the ingress buffers for the N320 radio to
support 250MHz TX streaming rates.
Signed-off-by: mattprost <matt.prost@ni.com>
Original-commit: e8db6fa4301ce471bf41ef14d5d38e5727199007
This adds new image files which come with a DRAM FIFO. The addition of
an N320 image with a DRAM FIFO allows DDR3 BIST to be run on an
assembled (motherboard + daughterboard) N320.
This image is intentionally very similar to the N300_AA and N310_AA
targets which serve the same purpose of providing an image with a DRAM
FIFO for their respective devices.
Original-commit: ae2b9bf7aeea6f8f98f6dacffdfc018d87107927
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
- Fixed some incorrect comments
- Fixed some missing wire declarations for internal NIC
- Fix wire declarations for GPIO (they were declared too late)
Original-commit: b18eaa75de2d1dcba2a1be0ee0b862a57e976cca
The address ranges configured for the AXI interconnect IP limited the
amount of accessible DRAM to two 32 MB regions. This change makes the
full 1G available to all DRAM ports.
Original-commit: bba0cddfadcb744e8a6fae27d57ba8d3995eaf64
Humberto Jimenez