fpga: x400: zbx: Add support for ZBX CPLD
Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Original-commit: 99b841c75aa91709090cbf4046bf51b7ffb4f612
This commit is contained in:
Javier Valenzuela
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Cherwa Vang
Martin Braun
Max Köhler
Paul Butler
Cherwa Vang
Martin Braun
Max Köhler
Paul Butler
parent
7e59e9516d
commit
a1d7c252c2
@@ -0,0 +1,7 @@
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# Ignore Quartus generated files upon project opening.
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*.qws
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db/
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doc/*.xml
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incremental_db/
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output_files/
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*.sopcinfo
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@@ -0,0 +1,90 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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GIT_HASH = $(shell ../../../../../tools/scripts/git-hash.sh)
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build: cpld_defaults ip
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@echo -ne "\n---- Make: Synthesis ...\n\n";
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@quartus_map zbx_top_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)";
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@echo -ne "\n\n---- Make: Implementation ...\n\n";
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@quartus_fit zbx_top_cpld;
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@echo -ne "\n\n---- Make: Analyzing timing ...\n\n";
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@quartus_sta zbx_top_cpld;
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@# grep for unconstrained path warning
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@grep "332102" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# grep for timing closure critical warning
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@grep "332148" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# expect no warnings
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@grep -iw "warning" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# expect no critical warning except "review power analyzer report file"
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@grep -i "critical warning" output_files/* | grep -v 16562; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@echo -ne "\n\n---- Make: Generating bitfile...\n\n";
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@quartus_asm zbx_top_cpld;
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@echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n";
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@quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_on.svf -o background_programming=on;
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@echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n";
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@quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_off.svf;
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@echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n";
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@quartus_cpf -c raw_conversion.cof
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@echo -ne "\n\n---- Make: Copy final files...\n\n";
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@mkdir -p build
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@cp output_files/zbx_top_cpld.pof build/usrp_zbx_cpld.pof
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@cp output_files/zbx_top_cpld_isp_off.svf build/usrp_zbx_cpld.svf
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@cp output_files/zbx_top_cpld_isp_on.svf build/usrp_zbx_cpld_isp_on.svf
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@cp output_files/zbx_top_cpld_converted_cfm0_auto.rpd build/usrp_zbx_cpld.rpd
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@echo -ne "\n\n---- Make: ZBX CPLD ready!\n";
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@echo -ne " Use build/usrp_zbx_cpld.pof via JTAG programmer or\n"
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@echo -ne " build/usrp_zbx_cpld.svf (ISP off) via MB CPLD JTAG engine or\n"
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@echo -ne " build/usrp_zbx_cpld.rpd via reconfig engine or\n"
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@echo -ne " build/usrp_zbx_cpld_isp_on.rpd via MB CPLD JTAG engine.\n"
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clean:
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@echo -ne "\nCleaning ZBX CPLD...\n";
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@git clean -Xdf
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QSYS_PATH=$(subst \,/,$(QUARTUS_ROOTDIR))/sopc_builder/bin
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ROOT_DIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))
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REGS_PY_FILE=$(ROOT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py
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REGS_PY_MODULE=register_endpoints/memory_init_files/zbx_cpld_regs_t.py
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$(REGS_PY_MODULE): $(REGS_PY_FILE)
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@python3 $(REGS_PY_FILE) $(REGS_PY_MODULE)
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# Using one of the files as a dependency (all files are generated at the same time)
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INIT_FILES := $(ROOT_DIR)/register_endpoints/memory_init_files/rx0_path_defaults.hex
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$(INIT_FILES): register_endpoints/memory_init_files/gen_defaults.py $(REGS_PY_MODULE)
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@python3 $(ROOT_DIR)/register_endpoints/memory_init_files/gen_defaults.py
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cpld_defaults: $(INIT_FILES)
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ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \
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ip/osc/osc/simulation/osc.v
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@make -C ../../../cpld ip
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ip/flash/on_chip_flash/simulation/on_chip_flash.v:
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$(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG
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ip/osc/osc/simulation/osc.v:
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$(QSYS_PATH)/qsys-generate ip/osc/osc.qsys --simulation=VERILOG
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all: build
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.PHONY: all build clean ip
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@@ -0,0 +1,73 @@
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_window
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//
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// Description:
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// Copy requests from slave to master interface when s_ctrlport_req_addr is in
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// address range specified by BASE_ADDRESS and WINDOW_SIZE. The modules does
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// not use any registers and therefore does not need ctrlport_clk and
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// ctrlport_rst.
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//
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`default_nettype none
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module ctrlport_window #(
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parameter BASE_ADDRESS = 0,
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parameter WINDOW_SIZE = 32
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) (
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// Slave Interface
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// Master Interface
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [ 9:0] m_ctrlport_req_portid,
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output wire [15:0] m_ctrlport_req_rem_epid,
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output wire [ 9:0] m_ctrlport_req_rem_portid,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_ctrlport_req_has_time,
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output wire [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data
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);
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// Mask write and read flag
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + WINDOW_SIZE);
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assign m_ctrlport_req_wr = s_ctrlport_req_wr & address_in_range;
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assign m_ctrlport_req_rd = s_ctrlport_req_rd & address_in_range;
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// Forward all other signals untouched.
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assign m_ctrlport_req_addr = s_ctrlport_req_addr;
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assign m_ctrlport_req_portid = s_ctrlport_req_portid;
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assign m_ctrlport_req_rem_epid = s_ctrlport_req_rem_epid;
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assign m_ctrlport_req_rem_portid = s_ctrlport_req_rem_portid;
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assign m_ctrlport_req_data = s_ctrlport_req_data;
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assign m_ctrlport_req_byte_en = s_ctrlport_req_byte_en;
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assign m_ctrlport_req_has_time = s_ctrlport_req_has_time;
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assign m_ctrlport_req_time = s_ctrlport_req_time;
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assign s_ctrlport_resp_ack = m_ctrlport_resp_ack;
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assign s_ctrlport_resp_status = m_ctrlport_resp_status;
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assign s_ctrlport_resp_data = m_ctrlport_resp_data;
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endmodule
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`default_nettype wire
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@@ -0,0 +1,10 @@
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<HTML>
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<HEAD>
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<title>ZBX_CPLD</title>
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<FRAMESET COLS="20%,*" onload=window.frames[1].location.hash=window.location.href.split("#")[1];>
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<FRAME name="leftframe" SRC="ZBX_CPLD_left.htm">
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<FRAME name="rightframe" SRC="ZBX_CPLD_right.htm">
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</FRAMESET>
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</HEAD>
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</HTML>
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@@ -0,0 +1,338 @@
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<html>
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<head>
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<meta http-equiv="Content-Type" content="text/html;charset=utf-8"/>
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<style type="text/css">
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body {
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margin: 5px;
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font-family: verdana, "Trebuchet MS", arial, helvetica, sans-serif;
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font-size: 80%;
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line-height: 1.3;
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}
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pre, code {
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font-family: "courier new", courier, monospace;
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font-size: 12px;
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}
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@media print {
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body {
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margin: 0px;
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font-family: arial, helvetica, sans-serif;
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font-size: 80%;
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line-height: 1;
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}
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} div.nav {
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font-size: 95%;
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}
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div.sh {
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display: none;
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margin-left: 15px;
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}
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div.shr {
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display: block;
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margin-left: 15px;
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}
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div.nav span.pm, div.nav span.pm_2 {
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color: black;
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font-family: courier new, courier;
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margin-right: 5px;
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}
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div.nav span.pm {
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cursor: pointer;
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}
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div.nav p {
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margin: 0px;
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padding: 0px;
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white-space: nowrap;
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}
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div.nav span {
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cursor: pointer;
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}
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div.nav span.regmap {
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color: #000080;
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}
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div.nav span.group {
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color: #006000;
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}
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div.nav span.enum {
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color: #800000;
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margin-left: 10px;
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}
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div.nav span.register {
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color: #004040;
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margin-left: 10px;
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}
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</style>
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<script type="text/javascript">
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function toggleText( id, sign ) {
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if (sign == "nochange") return;
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if ( document.getElementById )
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elem = document.getElementById( id );
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else if ( document.all )
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elem = eval( "document.all." + id );
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if (elem) {
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elemStyle = elem.style;
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if (sign=="+") {
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elemStyle.display = "block"
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} else {
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elemStyle.display = "none"
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}
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/*if ( elemStyle.display == "block" ) {
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elemStyle.display = "none"
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} else {
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elemStyle.display = "block"
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}*/
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}
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}
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function changePm( id ) {
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if ( document.getElementById )
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elem = document.getElementById( id );
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else if ( document.all )
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elem = eval( "document.all." + id );
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else
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return "nochange";
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var val = elem.innerHTML;
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if (val == "+") {
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elem.innerHTML = "-";
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} else {
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elem.innerHTML = "+";
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}
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return val;
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}
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function pm( id ) {
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var sign = changePm("pm_" + id);
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toggleText("div_" + id, sign);
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}
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function a( id ) {
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var currentURL= document.URL;
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var targetURL = currentURL.replace("_left", "_right");
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parent.frames[1].location = targetURL + '#' + id;
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}
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</script>
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</head><body>
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<div class="nav">
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<p>
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<span class="pm" id="pm_ZBX_CPLD" onclick="pm('ZBX_CPLD');">+</span>
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<span class="regmap" id="a_ZBX_CPLD" onclick="a('ZBX_CPLD');">ZBX_CPLD</span>
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</p>
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<div class="sh" id="div_ZBX_CPLD">
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<p>
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<span class="pm" id="pm_P1 Content" onclick="pm('P1 Content');">+</span>
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<span class="group" id="a_P1 Content" onclick="a('P1 Content');">P1 Content</span>
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</p>
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<div class="sh" id="div_P1 Content">
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</div>
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<p>
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<span class="pm" id="pm_ports" onclick="pm('ports');">+</span>
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<span class="group" id="a_ports" onclick="a('ports');">ports</span>
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</p>
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<div class="sh" id="div_ports">
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<p><span class="register" id="a_ZBX_CPLD|GPIO" onclick="a('ZBX_CPLD|GPIO');">GPIO</span></p>
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<p><span class="register" id="a_ZBX_CPLD|SPI" onclick="a('ZBX_CPLD|SPI');">SPI</span></p>
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</div>
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</div>
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<p>
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<span class="pm" id="pm_ATR_REGMAP" onclick="pm('ATR_REGMAP');">+</span>
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<span class="regmap" id="a_ATR_REGMAP" onclick="a('ATR_REGMAP');">ATR_REGMAP</span>
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</p> <div class="sh" id="div_ATR_REGMAP">
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<p>
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<span class="pm" id="pm_ATR_REGMAP|ATR_REGISTERS" onclick="pm('ATR_REGMAP|ATR_REGISTERS');">+</span>
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<span class="group" id="a_ATR_REGMAP|ATR_REGISTERS" onclick="a('ATR_REGMAP|ATR_REGISTERS');">ATR_REGISTERS</span>
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</p>
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<div class="sh" id="div_ATR_REGMAP|ATR_REGISTERS">
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<p><span class="enum" id="a_ATR_REGMAP|ATR_OPTIONS" onclick="a('ATR_REGMAP|ATR_OPTIONS');">enum ATR_OPTIONS</span></p>
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<p><span class="register" id="a_ATR_REGMAP|CURRENT_CONFIG_REG" onclick="a('ATR_REGMAP|CURRENT_CONFIG_REG');">CURRENT_CONFIG_REG</span></p>
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<p><span class="register" id="a_ATR_REGMAP|OPTION_REG" onclick="a('ATR_REGMAP|OPTION_REG');">OPTION_REG</span></p>
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<p><span class="register" id="a_ATR_REGMAP|SW_CONFIG_REG" onclick="a('ATR_REGMAP|SW_CONFIG_REG');">SW_CONFIG_REG</span></p>
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</div>
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</div>
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<p>
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<span class="pm" id="pm_BASIC_REGS_REGMAP" onclick="pm('BASIC_REGS_REGMAP');">+</span>
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<span class="regmap" id="a_BASIC_REGS_REGMAP" onclick="a('BASIC_REGS_REGMAP');">BASIC_REGS_REGMAP</span>
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</p> <div class="sh" id="div_BASIC_REGS_REGMAP">
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<p>
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<span class="pm" id="pm_BASIC_REGS_REGMAP|BASIC_REGS_REGISTERS" onclick="pm('BASIC_REGS_REGMAP|BASIC_REGS_REGISTERS');">+</span>
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<span class="group" id="a_BASIC_REGS_REGMAP|BASIC_REGS_REGISTERS" onclick="a('BASIC_REGS_REGMAP|BASIC_REGS_REGISTERS');">BASIC_REGS_REGISTERS</span>
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</p>
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<div class="sh" id="div_BASIC_REGS_REGMAP|BASIC_REGS_REGISTERS">
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<p><span class="enum" id="a_BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES" onclick="a('BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES');">enum BASIC_REGISTERS_VALUES</span></p>
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<p><span class="register" id="a_BASIC_REGS_REGMAP|SLAVE_SIGNATURE" onclick="a('BASIC_REGS_REGMAP|SLAVE_SIGNATURE');">SLAVE_SIGNATURE</span></p>
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<p><span class="register" id="a_BASIC_REGS_REGMAP|SLAVE_REVISION" onclick="a('BASIC_REGS_REGMAP|SLAVE_REVISION');">SLAVE_REVISION</span></p>
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<p><span class="register" id="a_BASIC_REGS_REGMAP|SLAVE_OLDEST_REVISION" onclick="a('BASIC_REGS_REGMAP|SLAVE_OLDEST_REVISION');">SLAVE_OLDEST_REVISION</span></p>
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<p><span class="register" id="a_BASIC_REGS_REGMAP|SLAVE_SCRATCH" onclick="a('BASIC_REGS_REGMAP|SLAVE_SCRATCH');">SLAVE_SCRATCH</span></p>
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<p><span class="register" id="a_BASIC_REGS_REGMAP|GIT_HASH_REGISTER" onclick="a('BASIC_REGS_REGMAP|GIT_HASH_REGISTER');">GIT_HASH_REGISTER</span></p>
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</div>
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</div>
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<p>
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<span class="pm" id="pm_DB_CONTROL_REGMAP" onclick="pm('DB_CONTROL_REGMAP');">+</span>
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<span class="regmap" id="a_DB_CONTROL_REGMAP" onclick="a('DB_CONTROL_REGMAP');">DB_CONTROL_REGMAP</span>
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</p> <div class="sh" id="div_DB_CONTROL_REGMAP">
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<p>
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<span class="pm" id="pm_DB_CONTROL_REGMAP|DB_CONTROL_WINDOWS" onclick="pm('DB_CONTROL_REGMAP|DB_CONTROL_WINDOWS');">+</span>
|
||||
<span class="group" id="a_DB_CONTROL_REGMAP|DB_CONTROL_WINDOWS" onclick="a('DB_CONTROL_REGMAP|DB_CONTROL_WINDOWS');">DB_CONTROL_WINDOWS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_DB_CONTROL_REGMAP|DB_CONTROL_WINDOWS">
|
||||
<p><span class="register" id="a_DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS" onclick="a('DB_CONTROL_REGMAP|ATR_CONTROLLER_REGS');">ATR_CONTROLLER_REGS</span></p>
|
||||
<p><span class="register" id="a_DB_CONTROL_REGMAP|LO_CONTROL_REGS" onclick="a('DB_CONTROL_REGMAP|LO_CONTROL_REGS');">LO_CONTROL_REGS</span></p>
|
||||
<p><span class="register" id="a_DB_CONTROL_REGMAP|LED_SETUP_REGS" onclick="a('DB_CONTROL_REGMAP|LED_SETUP_REGS');">LED_SETUP_REGS</span></p>
|
||||
<p><span class="register" id="a_DB_CONTROL_REGMAP|SWITCH_SETUP_REGS" onclick="a('DB_CONTROL_REGMAP|SWITCH_SETUP_REGS');">SWITCH_SETUP_REGS</span></p>
|
||||
<p><span class="register" id="a_DB_CONTROL_REGMAP|DSA_SETUP_REGS" onclick="a('DB_CONTROL_REGMAP|DSA_SETUP_REGS');">DSA_SETUP_REGS</span></p>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_DB_CONTROL_REGMAP|REGISTER_ENDPOINTS" onclick="pm('DB_CONTROL_REGMAP|REGISTER_ENDPOINTS');">+</span>
|
||||
<span class="group" id="a_DB_CONTROL_REGMAP|REGISTER_ENDPOINTS" onclick="a('DB_CONTROL_REGMAP|REGISTER_ENDPOINTS');">REGISTER_ENDPOINTS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_DB_CONTROL_REGMAP|REGISTER_ENDPOINTS">
|
||||
<p><span class="enum" id="a_DB_CONTROL_REGMAP|REGISTER_BLOCKS" onclick="a('DB_CONTROL_REGMAP|REGISTER_BLOCKS');">enum REGISTER_BLOCKS</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_DSA_SETUP_REGMAP" onclick="pm('DSA_SETUP_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_DSA_SETUP_REGMAP" onclick="a('DSA_SETUP_REGMAP');">DSA_SETUP_REGMAP</span>
|
||||
</p> <div class="sh" id="div_DSA_SETUP_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_DSA_SETUP_REGMAP|DSA_SETUP_REGISTERS" onclick="pm('DSA_SETUP_REGMAP|DSA_SETUP_REGISTERS');">+</span>
|
||||
<span class="group" id="a_DSA_SETUP_REGMAP|DSA_SETUP_REGISTERS" onclick="a('DSA_SETUP_REGMAP|DSA_SETUP_REGISTERS');">DSA_SETUP_REGISTERS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_DSA_SETUP_REGMAP|DSA_SETUP_REGISTERS">
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|TX0_DSA_ATR" onclick="a('DSA_SETUP_REGMAP|TX0_DSA_ATR');">TX0_DSA_ATR</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|TX1_DSA_ATR" onclick="a('DSA_SETUP_REGMAP|TX1_DSA_ATR');">TX1_DSA_ATR</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|RX0_DSA_ATR" onclick="a('DSA_SETUP_REGMAP|RX0_DSA_ATR');">RX0_DSA_ATR</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|RX1_DSA_ATR" onclick="a('DSA_SETUP_REGMAP|RX1_DSA_ATR');">RX1_DSA_ATR</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT" onclick="a('DSA_SETUP_REGMAP|TX0_DSA_TABLE_SELECT');">TX0_DSA_TABLE_SELECT</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT" onclick="a('DSA_SETUP_REGMAP|TX1_DSA_TABLE_SELECT');">TX1_DSA_TABLE_SELECT</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT" onclick="a('DSA_SETUP_REGMAP|RX0_DSA_TABLE_SELECT');">RX0_DSA_TABLE_SELECT</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT" onclick="a('DSA_SETUP_REGMAP|RX1_DSA_TABLE_SELECT');">RX1_DSA_TABLE_SELECT</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|TX0_DSA_TABLE" onclick="a('DSA_SETUP_REGMAP|TX0_DSA_TABLE');">TX0_DSA_TABLE</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|TX1_DSA_TABLE" onclick="a('DSA_SETUP_REGMAP|TX1_DSA_TABLE');">TX1_DSA_TABLE</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|RX0_DSA_TABLE" onclick="a('DSA_SETUP_REGMAP|RX0_DSA_TABLE');">RX0_DSA_TABLE</span></p>
|
||||
<p><span class="register" id="a_DSA_SETUP_REGMAP|RX1_DSA_TABLE" onclick="a('DSA_SETUP_REGMAP|RX1_DSA_TABLE');">RX1_DSA_TABLE</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_GPIO_REGMAP" onclick="pm('GPIO_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_GPIO_REGMAP" onclick="a('GPIO_REGMAP');">GPIO_REGMAP</span>
|
||||
</p> <div class="sh" id="div_GPIO_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_GPIO_REGMAP|GPIO_REGMAP_WINDOWS" onclick="pm('GPIO_REGMAP|GPIO_REGMAP_WINDOWS');">+</span>
|
||||
<span class="group" id="a_GPIO_REGMAP|GPIO_REGMAP_WINDOWS" onclick="a('GPIO_REGMAP|GPIO_REGMAP_WINDOWS');">GPIO_REGMAP_WINDOWS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_GPIO_REGMAP|GPIO_REGMAP_WINDOWS">
|
||||
<p><span class="register" id="a_GPIO_REGMAP|BASE_WINDOW_GPIO" onclick="a('GPIO_REGMAP|BASE_WINDOW_GPIO');">BASE_WINDOW_GPIO</span></p>
|
||||
<p><span class="register" id="a_GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO" onclick="a('GPIO_REGMAP|DB_CONTROL_WINDOW_GPIO');">DB_CONTROL_WINDOW_GPIO</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_LED_SETUP_REGMAP" onclick="pm('LED_SETUP_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_LED_SETUP_REGMAP" onclick="a('LED_SETUP_REGMAP');">LED_SETUP_REGMAP</span>
|
||||
</p> <div class="sh" id="div_LED_SETUP_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_LED_SETUP_REGMAP|LED_SETUP_REGISTERS" onclick="pm('LED_SETUP_REGMAP|LED_SETUP_REGISTERS');">+</span>
|
||||
<span class="group" id="a_LED_SETUP_REGMAP|LED_SETUP_REGISTERS" onclick="a('LED_SETUP_REGMAP|LED_SETUP_REGISTERS');">LED_SETUP_REGISTERS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_LED_SETUP_REGMAP|LED_SETUP_REGISTERS">
|
||||
<p><span class="register" id="a_LED_SETUP_REGMAP|LED_CONTROL" onclick="a('LED_SETUP_REGMAP|LED_CONTROL');">LED_CONTROL</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_LO_CONTROL_REGMAP" onclick="pm('LO_CONTROL_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_LO_CONTROL_REGMAP" onclick="a('LO_CONTROL_REGMAP');">LO_CONTROL_REGMAP</span>
|
||||
</p> <div class="sh" id="div_LO_CONTROL_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_LO_CONTROL_REGMAP|LO_SPI_REGISTERS" onclick="pm('LO_CONTROL_REGMAP|LO_SPI_REGISTERS');">+</span>
|
||||
<span class="group" id="a_LO_CONTROL_REGMAP|LO_SPI_REGISTERS" onclick="a('LO_CONTROL_REGMAP|LO_SPI_REGISTERS');">LO_SPI_REGISTERS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_LO_CONTROL_REGMAP|LO_SPI_REGISTERS">
|
||||
<p><span class="enum" id="a_LO_CONTROL_REGMAP|LO_CHIP_SELECT" onclick="a('LO_CONTROL_REGMAP|LO_CHIP_SELECT');">enum LO_CHIP_SELECT</span></p>
|
||||
<p><span class="register" id="a_LO_CONTROL_REGMAP|LO_SPI_SETUP" onclick="a('LO_CONTROL_REGMAP|LO_SPI_SETUP');">LO_SPI_SETUP</span></p>
|
||||
<p><span class="register" id="a_LO_CONTROL_REGMAP|LO_SPI_STATUS" onclick="a('LO_CONTROL_REGMAP|LO_SPI_STATUS');">LO_SPI_STATUS</span></p>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_LO_CONTROL_REGMAP|LO_SYNC_REGS" onclick="pm('LO_CONTROL_REGMAP|LO_SYNC_REGS');">+</span>
|
||||
<span class="group" id="a_LO_CONTROL_REGMAP|LO_SYNC_REGS" onclick="a('LO_CONTROL_REGMAP|LO_SYNC_REGS');">LO_SYNC_REGS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_LO_CONTROL_REGMAP|LO_SYNC_REGS">
|
||||
<p><span class="register" id="a_LO_CONTROL_REGMAP|LO_PULSE_SYNC" onclick="a('LO_CONTROL_REGMAP|LO_PULSE_SYNC');">LO_PULSE_SYNC</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_POWER_REGS_REGMAP" onclick="pm('POWER_REGS_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_POWER_REGS_REGMAP" onclick="a('POWER_REGS_REGMAP');">POWER_REGS_REGMAP</span>
|
||||
</p> <div class="sh" id="div_POWER_REGS_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_POWER_REGS_REGMAP|POWER_REGS_REGISTERS" onclick="pm('POWER_REGS_REGMAP|POWER_REGS_REGISTERS');">+</span>
|
||||
<span class="group" id="a_POWER_REGS_REGMAP|POWER_REGS_REGISTERS" onclick="a('POWER_REGS_REGMAP|POWER_REGS_REGISTERS');">POWER_REGS_REGISTERS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_POWER_REGS_REGMAP|POWER_REGS_REGISTERS">
|
||||
<p><span class="register" id="a_POWER_REGS_REGMAP|RF_POWER_CONTROL" onclick="a('POWER_REGS_REGMAP|RF_POWER_CONTROL');">RF_POWER_CONTROL</span></p>
|
||||
<p><span class="register" id="a_POWER_REGS_REGMAP|RF_POWER_STATUS" onclick="a('POWER_REGS_REGMAP|RF_POWER_STATUS');">RF_POWER_STATUS</span></p>
|
||||
<p><span class="register" id="a_POWER_REGS_REGMAP|PRC_CONTROL" onclick="a('POWER_REGS_REGMAP|PRC_CONTROL');">PRC_CONTROL</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_RECONFIG_REGMAP" onclick="pm('RECONFIG_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_RECONFIG_REGMAP" onclick="a('RECONFIG_REGMAP');">RECONFIG_REGMAP</span>
|
||||
</p> <div class="sh" id="div_RECONFIG_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_RECONFIG_REGMAP|RECONFIG_REGS" onclick="pm('RECONFIG_REGMAP|RECONFIG_REGS');">+</span>
|
||||
<span class="group" id="a_RECONFIG_REGMAP|RECONFIG_REGS" onclick="a('RECONFIG_REGMAP|RECONFIG_REGS');">RECONFIG_REGS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_RECONFIG_REGMAP|RECONFIG_REGS">
|
||||
<p><span class="enum" id="a_RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM" onclick="a('RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM');">enum FLASH_PRIMARY_IMAGE_ADDR_ENUM</span></p>
|
||||
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_STATUS_REG" onclick="a('RECONFIG_REGMAP|FLASH_STATUS_REG');">FLASH_STATUS_REG</span></p>
|
||||
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CONTROL_REG" onclick="a('RECONFIG_REGMAP|FLASH_CONTROL_REG');">FLASH_CONTROL_REG</span></p>
|
||||
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_ADDR_REG');">FLASH_ADDR_REG</span></p>
|
||||
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_WRITE_DATA_REG" onclick="a('RECONFIG_REGMAP|FLASH_WRITE_DATA_REG');">FLASH_WRITE_DATA_REG</span></p>
|
||||
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_READ_DATA_REG" onclick="a('RECONFIG_REGMAP|FLASH_READ_DATA_REG');">FLASH_READ_DATA_REG</span></p>
|
||||
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_CFM0_START_ADDR_REG');">FLASH_CFM0_START_ADDR_REG</span></p>
|
||||
<p><span class="register" id="a_RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG" onclick="a('RECONFIG_REGMAP|FLASH_CFM0_END_ADDR_REG');">FLASH_CFM0_END_ADDR_REG</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_SPI_REGMAP" onclick="pm('SPI_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_SPI_REGMAP" onclick="a('SPI_REGMAP');">SPI_REGMAP</span>
|
||||
</p> <div class="sh" id="div_SPI_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_SPI_REGMAP|SPI_REGMAP_WINDOWS" onclick="pm('SPI_REGMAP|SPI_REGMAP_WINDOWS');">+</span>
|
||||
<span class="group" id="a_SPI_REGMAP|SPI_REGMAP_WINDOWS" onclick="a('SPI_REGMAP|SPI_REGMAP_WINDOWS');">SPI_REGMAP_WINDOWS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_SPI_REGMAP|SPI_REGMAP_WINDOWS">
|
||||
<p><span class="register" id="a_SPI_REGMAP|BASE_WINDOW_SPI" onclick="a('SPI_REGMAP|BASE_WINDOW_SPI');">BASE_WINDOW_SPI</span></p>
|
||||
<p><span class="register" id="a_SPI_REGMAP|RECONFIG" onclick="a('SPI_REGMAP|RECONFIG');">RECONFIG</span></p>
|
||||
<p><span class="register" id="a_SPI_REGMAP|POWER_REGS" onclick="a('SPI_REGMAP|POWER_REGS');">POWER_REGS</span></p>
|
||||
<p><span class="register" id="a_SPI_REGMAP|DB_CONTROL_WINDOW_SPI" onclick="a('SPI_REGMAP|DB_CONTROL_WINDOW_SPI');">DB_CONTROL_WINDOW_SPI</span></p>
|
||||
</div>
|
||||
</div>
|
||||
<p>
|
||||
<span class="pm" id="pm_SWITCH_SETUP_REGMAP" onclick="pm('SWITCH_SETUP_REGMAP');">+</span>
|
||||
<span class="regmap" id="a_SWITCH_SETUP_REGMAP" onclick="a('SWITCH_SETUP_REGMAP');">SWITCH_SETUP_REGMAP</span>
|
||||
</p> <div class="sh" id="div_SWITCH_SETUP_REGMAP">
|
||||
<p>
|
||||
<span class="pm" id="pm_SWITCH_SETUP_REGMAP|SWITCH_SETUP_REGISTERS" onclick="pm('SWITCH_SETUP_REGMAP|SWITCH_SETUP_REGISTERS');">+</span>
|
||||
<span class="group" id="a_SWITCH_SETUP_REGMAP|SWITCH_SETUP_REGISTERS" onclick="a('SWITCH_SETUP_REGMAP|SWITCH_SETUP_REGISTERS');">SWITCH_SETUP_REGISTERS</span>
|
||||
</p>
|
||||
<div class="sh" id="div_SWITCH_SETUP_REGMAP|SWITCH_SETUP_REGISTERS">
|
||||
<p><span class="register" id="a_SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL" onclick="a('SWITCH_SETUP_REGMAP|TX0_PATH_CONTROL');">TX0_PATH_CONTROL</span></p>
|
||||
<p><span class="register" id="a_SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL" onclick="a('SWITCH_SETUP_REGMAP|TX1_PATH_CONTROL');">TX1_PATH_CONTROL</span></p>
|
||||
<p><span class="register" id="a_SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL" onclick="a('SWITCH_SETUP_REGMAP|RX0_PATH_CONTROL');">RX0_PATH_CONTROL</span></p>
|
||||
<p><span class="register" id="a_SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL" onclick="a('SWITCH_SETUP_REGMAP|RX1_PATH_CONTROL');">RX1_PATH_CONTROL</span></p>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</body>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,3 @@
|
||||
# generate files
|
||||
on_chip_flash/
|
||||
on_chip_flash.sopcinfo
|
||||
@@ -0,0 +1,90 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags="INTERNAL_COMPONENT=true"
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element onchip_flash_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="10M04SAU324I7G" />
|
||||
<parameter name="deviceFamily" value="MAX 10" />
|
||||
<parameter name="deviceSpeedGrade" value="7" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="true" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="1" />
|
||||
<parameter name="projectName" value="" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface name="clk" internal="onchip_flash_0.clk" type="clock" dir="end">
|
||||
<port name="clock" internal="clock" />
|
||||
</interface>
|
||||
<interface name="csr" internal="onchip_flash_0.csr" type="avalon" dir="end">
|
||||
<port name="avmm_csr_addr" internal="avmm_csr_addr" />
|
||||
<port name="avmm_csr_read" internal="avmm_csr_read" />
|
||||
<port name="avmm_csr_writedata" internal="avmm_csr_writedata" />
|
||||
<port name="avmm_csr_write" internal="avmm_csr_write" />
|
||||
<port name="avmm_csr_readdata" internal="avmm_csr_readdata" />
|
||||
</interface>
|
||||
<interface name="data" internal="onchip_flash_0.data" type="avalon" dir="end">
|
||||
<port name="avmm_data_addr" internal="avmm_data_addr" />
|
||||
<port name="avmm_data_read" internal="avmm_data_read" />
|
||||
<port name="avmm_data_writedata" internal="avmm_data_writedata" />
|
||||
<port name="avmm_data_write" internal="avmm_data_write" />
|
||||
<port name="avmm_data_readdata" internal="avmm_data_readdata" />
|
||||
<port name="avmm_data_waitrequest" internal="avmm_data_waitrequest" />
|
||||
<port name="avmm_data_readdatavalid" internal="avmm_data_readdatavalid" />
|
||||
<port name="avmm_data_burstcount" internal="avmm_data_burstcount" />
|
||||
</interface>
|
||||
<interface name="nreset" internal="onchip_flash_0.nreset" type="reset" dir="end">
|
||||
<port name="reset_n" internal="reset_n" />
|
||||
</interface>
|
||||
<module
|
||||
name="onchip_flash_0"
|
||||
kind="altera_onchip_flash"
|
||||
version="18.1"
|
||||
enabled="1"
|
||||
autoexport="1">
|
||||
<parameter name="AUTO_CLOCK_RATE" value="0" />
|
||||
<parameter name="CLOCK_FREQUENCY" value="50.0" />
|
||||
<parameter name="CONFIGURATION_MODE">Single Compressed Image with Memory Initialization</parameter>
|
||||
<parameter name="CONFIGURATION_SCHEME">Internal Configuration</parameter>
|
||||
<parameter name="DATA_INTERFACE" value="Parallel" />
|
||||
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
||||
<parameter name="PART_NAME" value="10M04SAU324I7G" />
|
||||
<parameter name="READ_BURST_COUNT" value="8" />
|
||||
<parameter name="READ_BURST_MODE" value="Incrementing" />
|
||||
<parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Read and write,Read and write,Read and write</parameter>
|
||||
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash_0</parameter>
|
||||
<parameter name="initFlashContent" value="false" />
|
||||
<parameter name="initializationFileName">altera_onchip_flash.hex</parameter>
|
||||
<parameter name="initializationFileNameForSim">altera_onchip_flash.dat</parameter>
|
||||
<parameter name="useNonDefaultInitFile" value="false" />
|
||||
</module>
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
@@ -0,0 +1,3 @@
|
||||
# generate files
|
||||
osc/
|
||||
osc.sopcinfo
|
||||
@@ -0,0 +1,63 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags="INTERNAL_COMPONENT=true"
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element int_osc_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="10M04SAU324I7G" />
|
||||
<parameter name="deviceFamily" value="MAX 10" />
|
||||
<parameter name="deviceSpeedGrade" value="7" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="true" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="1" />
|
||||
<parameter name="projectName" value="" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface name="clkout" internal="int_osc_0.clkout" type="clock" dir="start">
|
||||
<port name="clkout" internal="clkout" />
|
||||
</interface>
|
||||
<interface name="oscena" internal="int_osc_0.oscena" type="conduit" dir="end">
|
||||
<port name="oscena" internal="oscena" />
|
||||
</interface>
|
||||
<module
|
||||
name="int_osc_0"
|
||||
kind="altera_int_osc"
|
||||
version="18.1"
|
||||
enabled="1"
|
||||
autoexport="1">
|
||||
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
|
||||
<parameter name="CLOCK_FREQUENCY_1" value="55" />
|
||||
<parameter name="CLOCK_FREQUENCY_2" value="77" />
|
||||
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
||||
<parameter name="PART_NAME" value="10M04SAU324I7G" />
|
||||
</module>
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
@@ -0,0 +1,39 @@
|
||||
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
|
||||
<cof>
|
||||
<output_filename>output_files/zbx_top_cpld_converted.pof</output_filename>
|
||||
<n_pages>1</n_pages>
|
||||
<width>1</width>
|
||||
<mode>14</mode>
|
||||
<sof_data>
|
||||
<user_name>Page_0</user_name>
|
||||
<page_flags>1</page_flags>
|
||||
<bit0>
|
||||
<sof_filename>output_files/zbx_top_cpld.sof<compress_bitstream>1</compress_bitstream></sof_filename>
|
||||
</bit0>
|
||||
</sof_data>
|
||||
<version>10</version>
|
||||
<create_cvp_file>0</create_cvp_file>
|
||||
<create_hps_iocsr>0</create_hps_iocsr>
|
||||
<auto_create_rpd>1</auto_create_rpd>
|
||||
<rpd_little_endian>1</rpd_little_endian>
|
||||
<options>
|
||||
<map_file>1</map_file>
|
||||
</options>
|
||||
<MAX10_device_options>
|
||||
<por>0</por>
|
||||
<io_pullup>1</io_pullup>
|
||||
<config_from_cfm0_only>0</config_from_cfm0_only>
|
||||
<isp_source>0</isp_source>
|
||||
<verify_protect>0</verify_protect>
|
||||
<epof>0</epof>
|
||||
<ufm_source>0</ufm_source>
|
||||
</MAX10_device_options>
|
||||
<advanced_options>
|
||||
<ignore_epcs_id_check>1</ignore_epcs_id_check>
|
||||
<ignore_condone_check>2</ignore_condone_check>
|
||||
<plc_adjustment>0</plc_adjustment>
|
||||
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>
|
||||
<post_device_bitstream_pad_bytes>-1</post_device_bitstream_pad_bytes>
|
||||
<bitslice_pre_padding>1</bitslice_pre_padding>
|
||||
</advanced_options>
|
||||
</cof>
|
||||
@@ -0,0 +1,10 @@
|
||||
# CPLD Default values
|
||||
|
||||
The memory of the CPLD is configured to set all the RF components to safe
|
||||
values. That means:
|
||||
- LEDs off
|
||||
- DSAs are set to maximum attenuation
|
||||
|
||||
The Python script `memory_init_files/gen_defaults.py` creates the .hex files
|
||||
that get read into the CPLD bitfile. This is run as part of the Makefile
|
||||
process, and the script does not have to be executed manually.
|
||||
@@ -0,0 +1,341 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: atr_controller
|
||||
//
|
||||
// Description:
|
||||
// Controller of the ATR state configuration for the other register endpoints.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module atr_controller #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
// Clock and reset
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
|
||||
// Response
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output reg [ 1:0] s_ctrlport_resp_status,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// ATR state of FPGA
|
||||
// Assumes the following assignment on the FPGA:
|
||||
// {tx_running[1], rx_running[1], tx_running[0], rx_running[0]}
|
||||
// where the array index indicates the RF chain.
|
||||
input wire [ 3:0] atr_fpga_state,
|
||||
|
||||
// derived configuration
|
||||
output reg [ 7:0] atr_config_dsa_rf0 = 8'b0,
|
||||
output reg [ 7:0] atr_config_dsa_rf1 = 8'b0,
|
||||
output reg [ 7:0] atr_config_rf0 = 8'b0,
|
||||
output reg [ 7:0] atr_config_rf1 = 8'b0
|
||||
);
|
||||
|
||||
`include "../regmap/atr_regmap_utils.vh"
|
||||
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Internal registers
|
||||
//----------------------------------------------------------
|
||||
reg [ RF0_OPTION_SIZE-1:0] option_rf0 = SW_DEFINED;
|
||||
reg [ RF1_OPTION_SIZE-1:0] option_rf1 = SW_DEFINED;
|
||||
reg [RF0_DSA_OPTION_SIZE-1:0] option_dsa_rf0 = SW_DEFINED;
|
||||
reg [RF1_DSA_OPTION_SIZE-1:0] option_dsa_rf1 = SW_DEFINED;
|
||||
|
||||
reg [ SW_RF0_CONFIG_SIZE-1:0] sw_atr_config_rf0 = {SW_RF0_CONFIG_SIZE {1'b0}};
|
||||
reg [ SW_RF1_CONFIG_SIZE-1:0] sw_atr_config_rf1 = {SW_RF1_CONFIG_SIZE {1'b0}};
|
||||
reg [SW_RF0_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf0 = {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
|
||||
reg [SW_RF1_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf1 = {SW_RF1_DSA_CONFIG_SIZE {1'b0}};
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//----------------------------------------------------------
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// reset internal registers and responses
|
||||
if (ctrlport_rst) begin
|
||||
option_rf0 <= SW_DEFINED;
|
||||
option_rf1 <= SW_DEFINED;
|
||||
option_dsa_rf0 <= SW_DEFINED;
|
||||
option_dsa_rf1 <= SW_DEFINED;
|
||||
|
||||
sw_atr_config_rf0 <= {SW_RF0_CONFIG_SIZE {1'b0}};
|
||||
sw_atr_config_rf1 <= {SW_RF1_CONFIG_SIZE {1'b0}};
|
||||
sw_atr_config_dsa_rf0 <= {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
|
||||
sw_atr_config_dsa_rf1 <= {SW_RF1_DSA_CONFIG_SIZE {1'b0}};
|
||||
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
end else begin
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport_req_wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + OPTION_REG: begin
|
||||
option_rf0 <= s_ctrlport_req_data[RF0_OPTION_MSB : RF0_OPTION];
|
||||
option_rf1 <= s_ctrlport_req_data[RF1_OPTION_MSB : RF1_OPTION];
|
||||
option_dsa_rf0 <= s_ctrlport_req_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION];
|
||||
option_dsa_rf1 <= s_ctrlport_req_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + SW_CONFIG_REG: begin
|
||||
sw_atr_config_rf0 <= s_ctrlport_req_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG];
|
||||
sw_atr_config_rf1 <= s_ctrlport_req_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG];
|
||||
sw_atr_config_dsa_rf0 <= s_ctrlport_req_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG];
|
||||
sw_atr_config_dsa_rf1 <= s_ctrlport_req_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// read requests
|
||||
end else if (s_ctrlport_req_rd) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + CURRENT_CONFIG_REG: begin
|
||||
s_ctrlport_resp_data[CURRENT_RF0_CONFIG_MSB : CURRENT_RF0_CONFIG] <= atr_config_rf0;
|
||||
s_ctrlport_resp_data[CURRENT_RF1_CONFIG_MSB : CURRENT_RF1_CONFIG] <= atr_config_rf1;
|
||||
s_ctrlport_resp_data[CURRENT_RF0_DSA_CONFIG_MSB : CURRENT_RF0_DSA_CONFIG] <= atr_config_dsa_rf0;
|
||||
s_ctrlport_resp_data[CURRENT_RF1_DSA_CONFIG_MSB : CURRENT_RF1_DSA_CONFIG] <= atr_config_dsa_rf1;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + OPTION_REG: begin
|
||||
s_ctrlport_resp_data[RF0_OPTION_MSB : RF0_OPTION] <= option_rf0;
|
||||
s_ctrlport_resp_data[RF1_OPTION_MSB : RF1_OPTION] <= option_rf1;
|
||||
s_ctrlport_resp_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION] <= option_dsa_rf0;
|
||||
s_ctrlport_resp_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION] <= option_dsa_rf1;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + SW_CONFIG_REG: begin
|
||||
s_ctrlport_resp_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG] <= sw_atr_config_rf0;
|
||||
s_ctrlport_resp_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG] <= sw_atr_config_rf1;
|
||||
s_ctrlport_resp_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG] <= sw_atr_config_dsa_rf0;
|
||||
s_ctrlport_resp_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG] <= sw_atr_config_dsa_rf1;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------------
|
||||
// derive configuration
|
||||
//----------------------------------------------------------
|
||||
always @(posedge ctrlport_clk) begin
|
||||
case (option_rf0)
|
||||
SW_DEFINED: begin
|
||||
atr_config_rf0 <= sw_atr_config_rf0;
|
||||
end
|
||||
CLASSIC_ATR: begin
|
||||
atr_config_rf0 <= {6'b0, atr_fpga_state[1:0]};
|
||||
end
|
||||
FPGA_STATE: begin
|
||||
atr_config_rf0 <= {4'b0, atr_fpga_state};
|
||||
end
|
||||
endcase
|
||||
|
||||
case (option_rf1)
|
||||
SW_DEFINED: begin
|
||||
atr_config_rf1 <= sw_atr_config_rf1;
|
||||
end
|
||||
CLASSIC_ATR: begin
|
||||
atr_config_rf1 <= {6'b0, atr_fpga_state[3:2]};
|
||||
end
|
||||
FPGA_STATE: begin
|
||||
atr_config_rf1 <= {4'b0, atr_fpga_state};
|
||||
end
|
||||
endcase
|
||||
|
||||
case (option_dsa_rf0)
|
||||
SW_DEFINED: begin
|
||||
atr_config_dsa_rf0 <= sw_atr_config_dsa_rf0;
|
||||
end
|
||||
CLASSIC_ATR: begin
|
||||
atr_config_dsa_rf0 <= {6'b0, atr_fpga_state[1:0]};
|
||||
end
|
||||
FPGA_STATE: begin
|
||||
atr_config_dsa_rf0 <= {4'b0, atr_fpga_state};
|
||||
end
|
||||
endcase
|
||||
|
||||
case (option_dsa_rf1)
|
||||
SW_DEFINED: begin
|
||||
atr_config_dsa_rf1 <= sw_atr_config_dsa_rf1;
|
||||
end
|
||||
CLASSIC_ATR: begin
|
||||
atr_config_dsa_rf1 <= {6'b0, atr_fpga_state[3:2]};
|
||||
end
|
||||
FPGA_STATE: begin
|
||||
atr_config_dsa_rf1 <= {4'b0, atr_fpga_state};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="ATR_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
||||
// <group name="ATR_REGISTERS">
|
||||
// <info>
|
||||
// This regmap contains settings for the active configuration of RF 0 and 1.
|
||||
// There are two sets of configurations. One set comprises RF switches and
|
||||
// LEDs, the other set comprises the attenuators (DSA).
|
||||
// </info>
|
||||
//
|
||||
// <enumeratedtype name="ATR_OPTIONS">
|
||||
// <info>
|
||||
// Contains the options available for RF 0 and RF 1. The chosen setting
|
||||
// affects how the active configuration of up to 8 bits is derived.
|
||||
// </info>
|
||||
// <value name="SW_DEFINED" integer="0">
|
||||
// <info>
|
||||
// Uses the respective value of @.SW_CONFIG_REG as configuration.
|
||||
// </info>
|
||||
// </value>
|
||||
// <value name="CLASSIC_ATR" integer="1">
|
||||
// <info>
|
||||
// This option assumes the FPGA state to be assigned with: Bit 0 = RF 0
|
||||
// RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3
|
||||
// = RF 1 TX running. The configuration for each RF chain is built
|
||||
// up of the 2 bits for the RF chain (4 possible states: IDLE, RX only,
|
||||
// TX only, TX/RX).
|
||||
// </info>0
|
||||
// </value>
|
||||
// <value name="FPGA_STATE" integer="2">
|
||||
// <info>
|
||||
// The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.
|
||||
// </info>
|
||||
// </value>
|
||||
// </enumeratedtype>
|
||||
//
|
||||
// <register name="CURRENT_CONFIG_REG" size="32" offset="0x00" attributes="Readable">
|
||||
// <info>
|
||||
// Contains the current active configuration.
|
||||
// </info>
|
||||
// <bitfield name="CURRENT_RF0_CONFIG" range="7..0" type="integer">
|
||||
// <info>
|
||||
// Current active configuration for switches and LEDs of RF 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CURRENT_RF1_CONFIG" range="15..8" type="integer">
|
||||
// <info>
|
||||
// Current active configuration for switches and LEDs of RF 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CURRENT_RF0_DSA_CONFIG" range="23..16" type="integer">
|
||||
// <info>
|
||||
// Current active configuration for DSAs of RF 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CURRENT_RF1_DSA_CONFIG" range="31..24" type="integer">
|
||||
// <info>
|
||||
// Current active configuration for DSAs of RF 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="OPTION_REG" size="32" offset="0x04" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// Set the option to be used for the RF chains.
|
||||
// </info>
|
||||
// <bitfield name="RF0_OPTION" range="1..0" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
|
||||
// <info>
|
||||
// Option used for switches and LEDs of RF 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RF1_OPTION" range="9..8" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
|
||||
// <info>
|
||||
// Option used for switches and LEDs of RF 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RF0_DSA_OPTION" range="17..16" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
|
||||
// <info>
|
||||
// Option used for DSAs of RF 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RF1_DSA_OPTION" range="25..24" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
|
||||
// <info>
|
||||
// Option used for DSAs of RF 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="SW_CONFIG_REG" size="32" offset="0x08" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// Contains the configuration to be applied in case SW_DEFINED option is
|
||||
// chosen.
|
||||
// </info>
|
||||
// <bitfield name="SW_RF0_CONFIG" range="7..0" type="integer" initialvalue="0">
|
||||
// <info>
|
||||
// SW defined configuration for switches and LEDs of RF 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SW_RF1_CONFIG" range="15..8" type="integer" initialvalue="0">
|
||||
// <info>
|
||||
// SW defined configuration for switches and LEDs of RF 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SW_RF0_DSA_CONFIG" range="23..16" type="integer" initialvalue="0">
|
||||
// <info>
|
||||
// SW defined configuration for DSAs of RF 0.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="SW_RF1_DSA_CONFIG" range="31..24" type="integer" initialvalue="0">
|
||||
// <info>
|
||||
// SW defined configuration for DSAs of RF 1.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,219 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: basic_regs
|
||||
//
|
||||
// Description:
|
||||
// Basic Registers to inform software about version and capabilities.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module basic_regs #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
// Response
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output reg [ 1:0] s_ctrlport_resp_status,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
//reg clk domain
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst
|
||||
);
|
||||
|
||||
`include "../regmap/basic_regs_regmap_utils.vh"
|
||||
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Internal registers
|
||||
//----------------------------------------------------------
|
||||
reg [SCRATCH_REG_SIZE-1:0] scratch_reg = {SCRATCH_REG_SIZE {1'b0}};
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//----------------------------------------------------------
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// reset internal registers and responses
|
||||
if (ctrlport_rst) begin
|
||||
scratch_reg <= {SCRATCH_REG_SIZE {1'b0}};
|
||||
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
end else begin
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport_req_wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + SLAVE_SCRATCH: begin
|
||||
scratch_reg <= s_ctrlport_req_data[ SCRATCH_REG_MSB : SCRATCH_REG];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// read requests
|
||||
end else if (s_ctrlport_req_rd) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + SLAVE_SIGNATURE: begin
|
||||
s_ctrlport_resp_data[BOARD_ID_MSB : BOARD_ID]
|
||||
<= BOARD_ID_VALUE[BOARD_ID_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + SLAVE_REVISION: begin
|
||||
s_ctrlport_resp_data[REVISION_REG_MSB : REVISION_REG]
|
||||
<= CPLD_REVISION[REVISION_REG_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + SLAVE_OLDEST_REVISION: begin
|
||||
s_ctrlport_resp_data[OLDEST_REVISION_REG_MSB : OLDEST_REVISION_REG]
|
||||
<= OLDEST_CPLD_REVISION[OLDEST_REVISION_REG_SIZE-1:0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + SLAVE_SCRATCH: begin
|
||||
s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg;
|
||||
end
|
||||
|
||||
|
||||
BASE_ADDRESS + GIT_HASH_REGISTER: begin
|
||||
`ifdef GIT_HASH
|
||||
s_ctrlport_resp_data <= `GIT_HASH;
|
||||
`else
|
||||
s_ctrlport_resp_data <= 32'hDEADBEEF;
|
||||
`endif
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="BASIC_REGS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
||||
// <group name="BASIC_REGS_REGISTERS" size="0x010">
|
||||
// <info>
|
||||
// This regmap contains the revision registers, signature register, a scratch register, and a slave control reg.
|
||||
// </info>
|
||||
//
|
||||
// <enumeratedtype name="BASIC_REGISTERS_VALUES" showhexvalue="true">
|
||||
// <info>
|
||||
// This enum is used to create the constants held in the basic registers in both verilog and vhdl.
|
||||
// </info>
|
||||
// <value name="BOARD_ID_VALUE" integer="0x4002"/>
|
||||
// <value name="CPLD_REVISION" integer="0x21031009"/>
|
||||
// <value name="OLDEST_CPLD_REVISION" integer="0x20110611"/>
|
||||
// </enumeratedtype>
|
||||
//
|
||||
// <register name="SLAVE_SIGNATURE" size="32" offset="0x00" attributes="Readable">
|
||||
// <info>
|
||||
// This register contains the unique signature of the DB. This signature is the same value as the one
|
||||
// stored on the board ID EEPROM
|
||||
// </info>
|
||||
// <bitfield name="BOARD_ID" range="15..0" type="integer">
|
||||
// <info>
|
||||
// Board ID corresponds to the las 16 digits of the daughterboard part number.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="SLAVE_REVISION" size="32" offset="0x04" attributes="Readable">
|
||||
// <info>
|
||||
// This register contains the revision number of the current build
|
||||
// </info>
|
||||
// <bitfield name="REVISION_REG" range="31..0" type="integer">
|
||||
// <info>
|
||||
// Returns the revision in YYMMDDHH format
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="SLAVE_OLDEST_REVISION" size="32" offset="0x08" attributes="Readable">
|
||||
// <info>
|
||||
// This register contains the revision number of the oldest compatible revision
|
||||
// </info>
|
||||
// <bitfield name="OLDEST_REVISION_REG" range="31..0" type="integer">
|
||||
// <info>
|
||||
// Returns the oldest compatible revision in YYMMDDHH format
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="SLAVE_SCRATCH" size="32" offset="0x0C" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// Read/write scratch register
|
||||
// </info>
|
||||
// <bitfield name="SCRATCH_REG" range="31..0" initialvalue="0">
|
||||
// <info>
|
||||
// Returns the value written here previously.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="GIT_HASH_REGISTER" offset="0x10" size="32" writable="false">
|
||||
// <info>
|
||||
// Git hash of commit used to build this image.{br}
|
||||
// Value equals 0xDEADBEEF if the git hash was not used during synthesis.
|
||||
// </info>
|
||||
// <bitfield name="GIT_CLEAN" range="31..28">
|
||||
// <info>
|
||||
// 0x0 in case the git status was clean{br}
|
||||
// 0xF in case there were uncommitted changes
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="GIT_HASH" range="27..0">
|
||||
// <info>7 hex digit hash code of the commit</info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,736 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: dsa_control
|
||||
//
|
||||
// Description:
|
||||
// Implements control over Digital Step Attenuators via CtrlPort. Uses RAM to
|
||||
// store multiple ATR configurations. Provides gain table to abstract from raw
|
||||
// DSA values.
|
||||
//
|
||||
// IMPORTANT: The default values here must be synchronized with the default
|
||||
// values in gen_defaults.py, they are not automatically kept in sync.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module dsa_control #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
// Clock and reset
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
|
||||
// Response
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
|
||||
output reg [31:0] s_ctrlport_resp_data = 32'b0,
|
||||
|
||||
// ATR switching
|
||||
input wire [ 7:0] atr_config_rf0,
|
||||
input wire [ 7:0] atr_config_rf1,
|
||||
|
||||
// The attenuation setting for TX paths is indexed from two,
|
||||
// to match schematic naming. In this case, the two LSBs
|
||||
// for parallel control going into the DSA chips are connected
|
||||
// to ground(those bits control fractional attenuation).
|
||||
|
||||
//Tx0 DSA control (domain: ctrl_reg_clk)
|
||||
output wire [6:2] tx0_dsa1,
|
||||
output wire [6:2] tx0_dsa2,
|
||||
|
||||
//Tx1 DSA control (domain: ctrl_reg_clk)
|
||||
output wire [6:2] tx1_dsa1,
|
||||
output wire [6:2] tx1_dsa2,
|
||||
|
||||
// The attenuation setting for RX paths is indexed from one,
|
||||
// to match schematic naming. In this case, the LSB controls
|
||||
// the highest value, so re reverse the order of the vector.
|
||||
// Note the these signals are active low.
|
||||
|
||||
//Rx0 DSA control (domain: ctrl_reg_clk)
|
||||
output wire [1:4] rx0_dsa1_n,
|
||||
output wire [1:4] rx0_dsa2_n,
|
||||
output wire [1:4] rx0_dsa3_a_n,
|
||||
output wire [1:4] rx0_dsa3_b_n,
|
||||
|
||||
//Rx1 DSA control (domain: ctrl_reg_clk)
|
||||
output wire [1:4] rx1_dsa1_n,
|
||||
output wire [1:4] rx1_dsa2_n,
|
||||
output wire [1:4] rx1_dsa3_a_n,
|
||||
output wire [1:4] rx1_dsa3_b_n
|
||||
);
|
||||
|
||||
`include "../regmap/dsa_setup_regmap_utils.vh"
|
||||
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// register bitfields
|
||||
//---------------------------------------------------------------
|
||||
reg [TX_DSA1_SIZE -1:0] tx0_dsa_1_reg = {TX_DSA1_SIZE{1'b1}};
|
||||
reg [TX_DSA2_SIZE -1:0] tx0_dsa_2_reg = {TX_DSA2_SIZE{1'b1}};
|
||||
|
||||
reg [TX_DSA1_SIZE -1:0] tx1_dsa_1_reg = {TX_DSA1_SIZE{1'b1}};
|
||||
reg [TX_DSA2_SIZE -1:0] tx1_dsa_2_reg = {TX_DSA2_SIZE{1'b1}};
|
||||
|
||||
reg [RX_DSA1_SIZE -1:0] rx0_dsa_1_reg = {RX_DSA1_SIZE{1'b1}};
|
||||
reg [RX_DSA2_SIZE -1:0] rx0_dsa_2_reg = {RX_DSA2_SIZE{1'b1}};
|
||||
reg [RX_DSA3_A_SIZE -1:0] rx0_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}};
|
||||
reg [RX_DSA3_B_SIZE -1:0] rx0_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}};
|
||||
|
||||
reg [RX_DSA1_SIZE -1:0] rx1_dsa_1_reg = {RX_DSA1_SIZE{1'b1}};
|
||||
reg [RX_DSA2_SIZE -1:0] rx1_dsa_2_reg = {RX_DSA2_SIZE{1'b1}};
|
||||
reg [RX_DSA3_A_SIZE -1:0] rx1_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}};
|
||||
reg [RX_DSA3_B_SIZE -1:0] rx1_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}};
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// ATR memory signals
|
||||
//---------------------------------------------------------------
|
||||
reg ram_tx0_wea = 1'b0;
|
||||
wire [31:0] ram_tx0_doa;
|
||||
wire [31:0] ram_tx0_dob;
|
||||
reg ram_tx1_wea = 1'b0;
|
||||
wire [31:0] ram_tx1_doa;
|
||||
wire [31:0] ram_tx1_dob;
|
||||
reg ram_rx0_wea = 1'b0;
|
||||
wire [31:0] ram_rx0_doa;
|
||||
wire [31:0] ram_rx0_dob;
|
||||
reg ram_rx1_wea = 1'b0;
|
||||
wire [31:0] ram_rx1_doa;
|
||||
wire [31:0] ram_rx1_dob;
|
||||
|
||||
reg table_tx0_wea = 1'b0;
|
||||
wire [31:0] table_tx0_doa;
|
||||
reg table_tx1_wea = 1'b0;
|
||||
wire [31:0] table_tx1_doa;
|
||||
reg table_rx0_wea = 1'b0;
|
||||
wire [31:0] table_rx0_doa;
|
||||
reg table_rx1_wea = 1'b0;
|
||||
wire [31:0] table_rx1_doa;
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//---------------------------------------------------------------
|
||||
// Check of request address is targeted for this module.
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
// Read request shift register to align memory read and response generation.
|
||||
reg [ 1:0] read_req_shift_reg = 2'b0;
|
||||
// Write request shift register to align gain table memory read and ATR memory
|
||||
// write operation.
|
||||
reg [ 1:0] write_req_shift_reg = 2'b0;
|
||||
// Mask out 8 bits for ATR configurations to be able to compare all ATR
|
||||
// configurations against the same base register address.
|
||||
wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};
|
||||
// Extract masked out bits from the address, which represent the register
|
||||
// array index = ATR configuration index
|
||||
wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];
|
||||
// switch between CtrlPort data and gain table data for ATR memories
|
||||
reg select_gain_table = 1'b0;
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// reset internal registers and responses
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
|
||||
read_req_shift_reg <= 2'b0;
|
||||
write_req_shift_reg <= 2'b0;
|
||||
|
||||
ram_tx0_wea <= 1'b0;
|
||||
ram_tx1_wea <= 1'b0;
|
||||
ram_rx0_wea <= 1'b0;
|
||||
ram_rx1_wea <= 1'b0;
|
||||
|
||||
table_tx0_wea <= 1'b0;
|
||||
table_tx1_wea <= 1'b0;
|
||||
table_rx0_wea <= 1'b0;
|
||||
table_rx1_wea <= 1'b0;
|
||||
|
||||
select_gain_table <= 1'b0;
|
||||
|
||||
end else begin
|
||||
// default assignments
|
||||
read_req_shift_reg <= { read_req_shift_reg[0], s_ctrlport_req_rd};
|
||||
write_req_shift_reg <= {write_req_shift_reg[0], s_ctrlport_req_wr};
|
||||
|
||||
ram_tx0_wea <= 1'b0;
|
||||
ram_tx1_wea <= 1'b0;
|
||||
ram_rx0_wea <= 1'b0;
|
||||
ram_rx1_wea <= 1'b0;
|
||||
|
||||
table_tx0_wea <= 1'b0;
|
||||
table_tx1_wea <= 1'b0;
|
||||
table_rx0_wea <= 1'b0;
|
||||
table_rx1_wea <= 1'b0;
|
||||
|
||||
select_gain_table <= 1'b0;
|
||||
|
||||
// Answer write requests delayed by 2 clock cycles. This compensated for
|
||||
// register ram_addr and the memory internal address register to make sure
|
||||
// gain table output data is up to date when forwarding data to ATR memory
|
||||
if (write_req_shift_reg[1]) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
case (register_base_address)
|
||||
BASE_ADDRESS + TX0_DSA_ATR(0): begin
|
||||
ram_tx0_wea <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + TX1_DSA_ATR(0): begin
|
||||
ram_tx1_wea <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + RX0_DSA_ATR(0): begin
|
||||
ram_rx0_wea <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + RX1_DSA_ATR(0): begin
|
||||
ram_rx1_wea <= 1'b1;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + TX0_DSA_TABLE(0): begin
|
||||
table_tx0_wea <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + TX1_DSA_TABLE(0): begin
|
||||
table_tx1_wea <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + RX0_DSA_TABLE(0): begin
|
||||
table_rx0_wea <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + RX1_DSA_TABLE(0): begin
|
||||
table_rx1_wea <= 1'b1;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0): begin
|
||||
ram_tx0_wea <= 1'b1;
|
||||
select_gain_table <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0): begin
|
||||
ram_tx1_wea <= 1'b1;
|
||||
select_gain_table <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0): begin
|
||||
ram_rx0_wea <= 1'b1;
|
||||
select_gain_table <= 1'b1;
|
||||
end
|
||||
BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin
|
||||
ram_rx1_wea <= 1'b1;
|
||||
select_gain_table <= 1'b1;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// Answer read requests delayed by 2 clock cycles. This compensated for
|
||||
// register ram_addr and the memory internal address register to make sure
|
||||
// ram_ch0_doa is up to date when generating the response.
|
||||
end else if (read_req_shift_reg[1]) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
|
||||
case (register_base_address)
|
||||
BASE_ADDRESS + TX0_DSA_ATR(0): begin
|
||||
s_ctrlport_resp_data <= ram_tx0_doa & TX_DSA_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + TX1_DSA_ATR(0): begin
|
||||
s_ctrlport_resp_data <= ram_tx1_doa & TX_DSA_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + RX0_DSA_ATR(0): begin
|
||||
s_ctrlport_resp_data <= ram_rx0_doa & RX_DSA_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + RX1_DSA_ATR(0): begin
|
||||
s_ctrlport_resp_data <= ram_rx1_doa & RX_DSA_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + TX0_DSA_TABLE(0): begin
|
||||
s_ctrlport_resp_data <= table_tx0_doa & TX_DSA_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + TX1_DSA_TABLE(0): begin
|
||||
s_ctrlport_resp_data <= table_tx1_doa & TX_DSA_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + RX0_DSA_TABLE(0): begin
|
||||
s_ctrlport_resp_data <= table_rx0_doa & RX_DSA_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + RX1_DSA_TABLE(0): begin
|
||||
s_ctrlport_resp_data <= table_rx1_doa & RX_DSA_CONTROL_MASK;
|
||||
end
|
||||
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// register without reset
|
||||
reg [ 7:0] ram_addr = 8'b0;
|
||||
reg [ 7:0] gain_table_addr = 8'b0;
|
||||
reg [31:0] ram_datain = 32'b0;
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// Capture CtrlPort data and address on requests as only in this clock cycle
|
||||
// the data is valid.
|
||||
if (s_ctrlport_req_wr || s_ctrlport_req_rd) begin
|
||||
ram_addr <= register_index;
|
||||
ram_datain <= s_ctrlport_req_data;
|
||||
|
||||
case (register_base_address)
|
||||
BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0),
|
||||
BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0),
|
||||
BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0),
|
||||
BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin
|
||||
gain_table_addr <= s_ctrlport_req_data[TABLE_INDEX_MSB:TABLE_INDEX];
|
||||
end
|
||||
default: begin
|
||||
gain_table_addr <= register_index;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// outputs
|
||||
tx0_dsa_1_reg <= ram_tx0_dob[ TX_DSA1_MSB : TX_DSA1];
|
||||
tx0_dsa_2_reg <= ram_tx0_dob[ TX_DSA2_MSB : TX_DSA2];
|
||||
|
||||
tx1_dsa_1_reg <= ram_tx1_dob[ TX_DSA1_MSB : TX_DSA1];
|
||||
tx1_dsa_2_reg <= ram_tx1_dob[ TX_DSA2_MSB : TX_DSA2];
|
||||
|
||||
rx0_dsa_1_reg <= ram_rx0_dob[ RX_DSA1_MSB : RX_DSA1];
|
||||
rx0_dsa_2_reg <= ram_rx0_dob[ RX_DSA2_MSB : RX_DSA2];
|
||||
rx0_dsa_3_a_reg <= ram_rx0_dob[RX_DSA3_A_MSB : RX_DSA3_A];
|
||||
rx0_dsa_3_b_reg <= ram_rx0_dob[RX_DSA3_B_MSB : RX_DSA3_B];
|
||||
|
||||
rx1_dsa_1_reg <= ram_rx1_dob[ RX_DSA1_MSB : RX_DSA1];
|
||||
rx1_dsa_2_reg <= ram_rx1_dob[ RX_DSA2_MSB : RX_DSA2];
|
||||
rx1_dsa_3_a_reg <= ram_rx1_dob[RX_DSA3_A_MSB : RX_DSA3_A];
|
||||
rx1_dsa_3_b_reg <= ram_rx1_dob[RX_DSA3_B_MSB : RX_DSA3_B];
|
||||
end
|
||||
|
||||
assign tx0_dsa1[6:2] = tx0_dsa_1_reg;
|
||||
assign tx0_dsa2[6:2] = tx0_dsa_2_reg;
|
||||
|
||||
assign tx1_dsa1[6:2] = tx1_dsa_1_reg;
|
||||
assign tx1_dsa2[6:2] = tx1_dsa_2_reg;
|
||||
|
||||
//Rx DSAs behave differently from Tx DSAs
|
||||
//Flip MSB/LSB, and invert
|
||||
|
||||
genvar vi;
|
||||
// take care of inverting the active low logic and bit-reversing
|
||||
// the DSA controls for RX paths.
|
||||
generate
|
||||
for (vi=1; vi<=4; vi=vi+1) begin : reverselogic
|
||||
// [1:4] [3:0]
|
||||
assign rx0_dsa1_n[vi] = !rx0_dsa_1_reg[4-vi];
|
||||
assign rx0_dsa2_n[vi] = !rx0_dsa_2_reg[4-vi];
|
||||
assign rx0_dsa3_a_n[vi] = !rx0_dsa_3_a_reg[4-vi];
|
||||
assign rx0_dsa3_b_n[vi] = !rx0_dsa_3_b_reg[4-vi];
|
||||
|
||||
assign rx1_dsa1_n[vi] = !rx1_dsa_1_reg[4-vi];
|
||||
assign rx1_dsa2_n[vi] = !rx1_dsa_2_reg[4-vi];
|
||||
assign rx1_dsa3_a_n[vi] = !rx1_dsa_3_a_reg[4-vi];
|
||||
assign rx1_dsa3_b_n[vi] = !rx1_dsa_3_b_reg[4-vi];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// ATR memories
|
||||
//---------------------------------------------------------------
|
||||
// Choose data source for ATR configurations from CtrlPort or gain table.
|
||||
wire [31:0] ram_rx0_dia = select_gain_table ? table_rx0_doa : ram_datain;
|
||||
wire [31:0] ram_rx1_dia = select_gain_table ? table_rx1_doa : ram_datain;
|
||||
wire [31:0] ram_tx0_dia = select_gain_table ? table_tx0_doa : ram_datain;
|
||||
wire [31:0] ram_tx1_dia = select_gain_table ? table_tx1_doa : ram_datain;
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
|
||||
) ram_tx0_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_tx0_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_tx0_dia),
|
||||
.doa (ram_tx0_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf0),
|
||||
.dib (0),
|
||||
.dob (ram_tx0_dob)
|
||||
);
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
|
||||
) ram_tx1_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_tx1_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_tx1_dia),
|
||||
.doa (ram_tx1_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf1),
|
||||
.dib (0),
|
||||
.dob (ram_tx1_dob)
|
||||
);
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
|
||||
) ram_rx0_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_rx0_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_rx0_dia),
|
||||
.doa (ram_rx0_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf0),
|
||||
.dib (0),
|
||||
.dob (ram_rx0_dob)
|
||||
);
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
|
||||
) ram_rx1_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_rx1_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_rx1_dia),
|
||||
.doa (ram_rx1_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf1),
|
||||
.dib (0),
|
||||
.dob (ram_rx1_dob)
|
||||
);
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// Gain tables
|
||||
//---------------------------------------------------------------
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
|
||||
) table_tx0_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (table_tx0_wea),
|
||||
.addra (gain_table_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (table_tx0_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (8'b0),
|
||||
.dib (32'b0),
|
||||
.dob ()
|
||||
);
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
|
||||
) table_tx1_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (table_tx1_wea),
|
||||
.addra (gain_table_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (table_tx1_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (8'b0),
|
||||
.dib (32'b0),
|
||||
.dob ()
|
||||
);
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
|
||||
) table_rx0_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (table_rx0_wea),
|
||||
.addra (gain_table_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (table_rx0_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (8'b0),
|
||||
.dib (32'b0),
|
||||
.dob ()
|
||||
);
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
|
||||
) table_rx1_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (table_rx1_wea),
|
||||
.addra (gain_table_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (table_rx1_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (8'b0),
|
||||
.dib (32'b0),
|
||||
.dob ()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="DSA_SETUP_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true" markdown="true">
|
||||
// <group name="DSA_SETUP_REGISTERS">
|
||||
// <info>
|
||||
// The following registers control the digital step attenuators (DSA).
|
||||
//
|
||||
// There are two ways to set the DSA values, which are applied to the DB ICs.
|
||||
//
|
||||
// 1. The ...DSA_ATR registers can be used to access the raw
|
||||
// values of each ATR configuration.
|
||||
//
|
||||
// 2. Gain tables can be used as intermediate step to abstract from the
|
||||
// raw DB values. This gain table can be modified using the ...DSA_TABLE
|
||||
// registers according to the content of the registers from the first
|
||||
// option. Initially each gain table is empty (all zeros). Each gain
|
||||
// table entry can be accessed at any time. Once the table is filled with
|
||||
// values the ...DSA_TABLE_SELECT registers can be used to get one gain
|
||||
// table entry with index TABLE_INDEX and write it to the appropriate ATR
|
||||
// configuration given by the address (see _show extended info_ link below
|
||||
// the register array headlines)
|
||||
// </info>
|
||||
// <regtype name="TX_DSA_CONTROL" size="32" attributes="Readable|Writable">
|
||||
// <bitfield name="TX_DSA1" range="4..0" initialvalue="31">
|
||||
// <info>
|
||||
// Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
|
||||
// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_DSA2" range="12..8" initialvalue="31">
|
||||
// <info>
|
||||
// Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the
|
||||
// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
//
|
||||
// <regtype name="RX_DSA_CONTROL" size="32" attributes="Readable|Writable">
|
||||
// <bitfield name="RX_DSA1" range="3..0" initialvalue="15">
|
||||
// <info>
|
||||
// Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
|
||||
// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_DSA2" range="7..4" initialvalue="15">
|
||||
// <info>
|
||||
// Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
|
||||
// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_DSA3_A" range="11..8" initialvalue="15">
|
||||
// <info>
|
||||
// Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
|
||||
// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_DSA3_B" range="15..12" initialvalue="15">
|
||||
// <info>
|
||||
// Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the
|
||||
// attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
//
|
||||
// <regtype name="DSA_TABLE_CONTROL" size="32" attributes="Writable">
|
||||
// <bitfield name="TABLE_INDEX" range="7..0">
|
||||
// <info>
|
||||
// Gain table index to be used for getting the raw attenuation values.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
//
|
||||
// <register name="TX0_DSA_ATR" offset="0x000" count="256" step="4" typename="TX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Controls the Tx0 DSAs by accessing the raw attenuation levels.
|
||||
//
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="TX1_DSA_ATR" offset="0x400" count="256" step="4" typename="TX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Controls the Tx1 DSAs by accessing the raw attenuation levels.
|
||||
//
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RX0_DSA_ATR" offset="0x800" count="256" step="4" typename="RX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Controls the Rx0 DSAs by accessing the raw attenuation levels.
|
||||
//
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="RX1_DSA_ATR" offset="0xC00" count="256" step="4" typename="RX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Controls the Rx1 DSAs by accessing the raw attenuation levels.
|
||||
//
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
//
|
||||
// <register name="TX0_DSA_TABLE_SELECT" offset="0x1000" count="256" step="4" typename="DSA_TABLE_CONTROL">
|
||||
// <info>
|
||||
// Controls the Tx0 DSAs by using the gain table to translate the table
|
||||
// index to raw attenuation levels. The register offset (i) is targeting
|
||||
// an ATR configuration to store the values from the gain table.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="TX1_DSA_TABLE_SELECT" offset="0x1400" count="256" step="4" typename="DSA_TABLE_CONTROL">
|
||||
// <info>
|
||||
// Controls the Tx1 DSAs by using the gain table to translate the table
|
||||
// index to raw attenuation levels. The register offset (i) is targeting
|
||||
// an ATR configuration to store the values from the gain table.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="RX0_DSA_TABLE_SELECT" offset="0x1800" count="256" step="4" typename="DSA_TABLE_CONTROL">
|
||||
// <info>
|
||||
// Controls the Rx0 DSAs by using the gain table to translate the table
|
||||
// index to raw attenuation levels. The register offset (i) is targeting
|
||||
// an ATR configuration to store the values from the gain table.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="RX1_DSA_TABLE_SELECT" offset="0x1C00" count="256" step="4" typename="DSA_TABLE_CONTROL">
|
||||
// <info>
|
||||
// Controls the Rx1 DSAs by using the gain table to translate the table
|
||||
// index to raw attenuation levels. The register offset (i) is targeting
|
||||
// an ATR configuration to store the values from the gain table.
|
||||
// </info>
|
||||
// </register>
|
||||
//
|
||||
// <register name="TX0_DSA_TABLE" offset="0x2000" count="256" step="4" typename="TX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Provides access to the gain table for Tx0.
|
||||
//
|
||||
// Each entry i will be saved in the gain table without any implications
|
||||
// on HW. Enables SW to use the table index in @.TX0_DSA_TABLE_SELECT to
|
||||
// modify the ATR configurations.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="TX1_DSA_TABLE" offset="0x2400" count="256" step="4" typename="TX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Provides access to the gain table for Tx1.
|
||||
//
|
||||
// Each entry i will be saved in the gain table without any implications
|
||||
// on HW. Enables SW to use the table index in @.TX1_DSA_TABLE_SELECT to
|
||||
// modify the ATR configurations.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="RX0_DSA_TABLE" offset="0x2800" count="256" step="4" typename="RX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Provides access to the gain table for Rx0.
|
||||
//
|
||||
// Each entry i will be saved in the gain table without any implications
|
||||
// on HW. Enables SW to use the table index in @.RX0_DSA_TABLE_SELECT to
|
||||
// modify the ATR configurations.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="RX1_DSA_TABLE" offset="0x2C00" count="256" step="4" typename="RX_DSA_CONTROL">
|
||||
// <info>
|
||||
// Provides access to the gain table for Rx1.
|
||||
//
|
||||
// Each entry i will be saved in the gain table without any implications
|
||||
// on HW. Enables SW to use the table index in @.RX1_DSA_TABLE_SELECT to
|
||||
// modify the ATR configurations.
|
||||
// </info>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,259 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: led_control
|
||||
//
|
||||
// Description:
|
||||
// Implements control over LED state via CtrlPort. The default state
|
||||
// has the LEDs disabled. Uses RAM to store multiple ATR configurations.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module led_control #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
// Clock and reset
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
// Response
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
|
||||
output reg [31:0] s_ctrlport_resp_data = 32'b0,
|
||||
|
||||
// LED Control (domain: ctrlport_clk)
|
||||
output reg ch0_rx2_led,
|
||||
output reg ch0_tx_led,
|
||||
output reg ch0_rx_led,
|
||||
output reg ch1_rx2_led,
|
||||
output reg ch1_tx_led,
|
||||
output reg ch1_rx_led,
|
||||
|
||||
// ATR switching
|
||||
input wire [ 7:0] atr_config_rf0,
|
||||
input wire [ 7:0] atr_config_rf1
|
||||
);
|
||||
|
||||
`include "../regmap/led_setup_regmap_utils.vh"
|
||||
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// ATR memory signals
|
||||
//---------------------------------------------------------------
|
||||
reg ram_ch0_wea;
|
||||
wire [31:0] ram_ch0_doa;
|
||||
wire [31:0] ram_ch0_dob;
|
||||
|
||||
reg ram_ch1_wea;
|
||||
wire [31:0] ram_ch1_dob;
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//---------------------------------------------------------------
|
||||
// Check of request address is targeted for this module.
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
// Read request shift register to align memory read and response generation.
|
||||
reg [ 1:0] read_req_shift_reg = 2'b0;
|
||||
// Mask out 8 bits for ATR configurations to be able to compare all ATR
|
||||
// configurations against the same base register address.
|
||||
wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};
|
||||
// Extract masked out bits from the address, which represent the register
|
||||
// array index = ATR configuration index
|
||||
wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// reset internal registers and responses
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
|
||||
read_req_shift_reg <= 2'b0;
|
||||
|
||||
ram_ch0_wea <= 1'b0;
|
||||
ram_ch1_wea <= 1'b0;
|
||||
|
||||
end else begin
|
||||
// default assignments
|
||||
read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};
|
||||
|
||||
ram_ch0_wea <= 1'b0;
|
||||
ram_ch1_wea <= 1'b0;
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport_req_wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
case (register_base_address)
|
||||
BASE_ADDRESS + LED_CONTROL(0): begin
|
||||
ram_ch0_wea <= 1'b1;
|
||||
ram_ch1_wea <= 1'b1;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// Answer read requests delayed by 2 clock cycles. This compensated for
|
||||
// register ram_addr and the memory internal address register to make sure
|
||||
// ram_ch0_doa is up to date when generating the response.
|
||||
end else if (read_req_shift_reg[1]) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
|
||||
case (register_base_address)
|
||||
BASE_ADDRESS + LED_CONTROL(0): begin
|
||||
s_ctrlport_resp_data <= ram_ch0_doa & LED_CONTROL_TYPE_MASK;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// register without reset
|
||||
reg [ 7:0] ram_addr = 8'b0;
|
||||
reg [31:0] ram_datain = 32'b0;
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// memories
|
||||
ram_addr <= register_index;
|
||||
ram_datain <= s_ctrlport_req_data;
|
||||
|
||||
//outputs
|
||||
ch0_rx2_led <= ram_ch0_dob[CH0_RX2_LED_EN];
|
||||
ch0_tx_led <= ram_ch0_dob[CH0_TRX1_LED_EN + 1];
|
||||
ch0_rx_led <= ram_ch0_dob[CH0_TRX1_LED_EN + 0];
|
||||
|
||||
ch1_rx2_led <= ram_ch1_dob[CH1_RX2_LED_EN];
|
||||
ch1_tx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 1];
|
||||
ch1_rx_led <= ram_ch1_dob[CH1_TRX1_LED_EN + 0];
|
||||
end
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("")
|
||||
) ram_ch0_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_ch0_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (ram_ch0_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf0),
|
||||
.dib (0),
|
||||
.dob (ram_ch0_dob)
|
||||
);
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("")
|
||||
) ram_ch1_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_ch1_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf1),
|
||||
.dib (0),
|
||||
.dob (ram_ch1_dob));
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="LED_SETUP_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
||||
// <group name="LED_SETUP_REGISTERS">
|
||||
// <info>
|
||||
// Contains registers that control the LEDs.
|
||||
// </info>
|
||||
// <regtype name="LED_CONTROL_TYPE" size="32" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// Defines LED functionality.
|
||||
// </info>
|
||||
// <bitfield name="CH0_RX2_LED_EN" range="0" initialvalue="0">
|
||||
// <info>
|
||||
// Enables the Ch0 Rx2 Green LED
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CH0_TRX1_LED_EN" range="2..1" initialvalue="0">
|
||||
// <info>
|
||||
// This bitfield controls the RG LED{BR/}
|
||||
// Bit 6 controls the Ch0 Rx Green LED{BR/}
|
||||
// Bit 7 controls the Ch0 Tx Red LED{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CH1_RX2_LED_EN" range="16" initialvalue="0">
|
||||
// <info>
|
||||
// Enables the Ch1 Rx2 Green LED
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CH1_TRX1_LED_EN" range="18..17" initialvalue="0">
|
||||
// <info>
|
||||
// This bitfield controls the RG LED{BR/}
|
||||
// Bit 15 controls the Ch1 Rx Green LED{BR/}
|
||||
// Bit 14 controls the Ch1 Tx Red LED{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
//
|
||||
// <register name="LED_CONTROL" offset="0x0" count="256" step="4" typename="LED_CONTROL_TYPE">
|
||||
// <info>
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,568 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: lo_control
|
||||
//
|
||||
// Description:
|
||||
// Implements control over signals interacting with LMX2572 chips on the
|
||||
// daughterboard. This includes a CtrlPort based control over a SPI master
|
||||
// that distributes transactions across the SPI buses of the LMX2572, as
|
||||
// well as the capability to synchronously generate pulses to their SYNC pins.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module lo_control #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
// Response
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output reg [ 1:0] s_ctrlport_resp_status,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
//reg clk domain
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// LO SPI for LMX2572
|
||||
input wire [7:0] miso,
|
||||
output reg [7:0] ss = {8{1'b1}},
|
||||
output wire sclk,
|
||||
output reg mosi = 1'b0,
|
||||
|
||||
// Incoming SYNC
|
||||
input wire mb_synth_sync,
|
||||
|
||||
// SYNC for LMX2572
|
||||
output wire tx0_lo1_sync,
|
||||
output wire tx0_lo2_sync,
|
||||
output wire tx1_lo1_sync,
|
||||
output wire tx1_lo2_sync,
|
||||
output wire rx0_lo1_sync,
|
||||
output wire rx0_lo2_sync,
|
||||
output wire rx1_lo1_sync,
|
||||
output wire rx1_lo2_sync
|
||||
);
|
||||
|
||||
`include "../regmap/lo_control_regmap_utils.vh"
|
||||
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// register bitfields
|
||||
//---------------------------------------------------------------
|
||||
|
||||
reg spi_start;
|
||||
reg [LO_SELECT_SIZE-1:0] spi_cs;
|
||||
reg spi_rd;
|
||||
reg [LO_SPI_WT_ADDR_SIZE-1:0] spi_addr;
|
||||
reg [LO_SPI_WT_DATA_SIZE-1:0] spi_data;
|
||||
reg spi_data_valid;
|
||||
reg spi_ready = 1'b1;
|
||||
reg [LO_SPI_RD_DATA_SIZE-1:0] spi_rd_data;
|
||||
reg [LO_CHIP_SELECT_SIZE-1:0] lo_sync_reg = 8'b0;
|
||||
reg bypass_sync = 1'b0;
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//---------------------------------------------------------------
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// reset internal registers and responses
|
||||
if (ctrlport_rst) begin
|
||||
spi_start <= 1'b0;
|
||||
spi_cs <= 3'b0;
|
||||
spi_rd <= 1'b0;
|
||||
spi_addr <= {LO_SPI_WT_ADDR_SIZE{1'b0}};
|
||||
spi_data <= {LO_SPI_WT_DATA_SIZE{1'b0}};
|
||||
lo_sync_reg <= 8'b0;
|
||||
bypass_sync <= 1'b0;
|
||||
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
end else begin
|
||||
|
||||
//send only a pulse
|
||||
spi_start <= 1'b0;
|
||||
|
||||
//pulse sync lines for a maximum of one cycle
|
||||
lo_sync_reg <= 8'b0;
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport_req_wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + LO_SPI_SETUP: begin
|
||||
spi_start <= s_ctrlport_req_data[LO_SPI_START_TRANSACTION];
|
||||
spi_cs <= s_ctrlport_req_data[LO_SELECT_MSB : LO_SELECT];
|
||||
spi_rd <= s_ctrlport_req_data[LO_SPI_RD];
|
||||
spi_addr <= s_ctrlport_req_data[LO_SPI_WT_ADDR_MSB : LO_SPI_WT_ADDR];
|
||||
spi_data <= s_ctrlport_req_data[LO_SPI_WT_DATA_MSB : LO_SPI_WT_DATA];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + LO_PULSE_SYNC: begin
|
||||
bypass_sync <= s_ctrlport_req_data[BYPASS_SYNC_REGISTER];
|
||||
lo_sync_reg[TX0_LO1] <= s_ctrlport_req_data[PULSE_TX0_LO1_SYNC];
|
||||
lo_sync_reg[TX0_LO2] <= s_ctrlport_req_data[PULSE_TX0_LO2_SYNC];
|
||||
lo_sync_reg[TX1_LO1] <= s_ctrlport_req_data[PULSE_TX1_LO1_SYNC];
|
||||
lo_sync_reg[TX1_LO2] <= s_ctrlport_req_data[PULSE_TX1_LO2_SYNC];
|
||||
lo_sync_reg[RX0_LO1] <= s_ctrlport_req_data[PULSE_RX0_LO1_SYNC];
|
||||
lo_sync_reg[RX0_LO2] <= s_ctrlport_req_data[PULSE_RX0_LO2_SYNC];
|
||||
lo_sync_reg[RX1_LO1] <= s_ctrlport_req_data[PULSE_RX1_LO1_SYNC];
|
||||
lo_sync_reg[RX1_LO2] <= s_ctrlport_req_data[PULSE_RX1_LO2_SYNC];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// read requests
|
||||
end else if (s_ctrlport_req_rd) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + LO_SPI_STATUS: begin //same address as *_status form regmap
|
||||
s_ctrlport_resp_data[LO_SPI_DATA_VALID] <= spi_data_valid;
|
||||
s_ctrlport_resp_data[LO_SELECT_MSB : LO_SELECT] <= spi_cs;
|
||||
s_ctrlport_resp_data[LO_SPI_READY] <= spi_ready;
|
||||
s_ctrlport_resp_data[LO_SPI_RD_ADDR_MSB : LO_SPI_RD_ADDR] <= spi_addr;
|
||||
s_ctrlport_resp_data[LO_SPI_RD_DATA_MSB : LO_SPI_RD_DATA] <= spi_rd_data;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Spi_top controls
|
||||
reg [4:0] wb_adr_i;
|
||||
reg wb_cyc_i;
|
||||
reg [31:0] wb_dat_i;
|
||||
reg wb_we_i;
|
||||
|
||||
// Spi_top outputs
|
||||
wire wb_ack_o;
|
||||
wire [31:0] wb_dat_o;
|
||||
wire wb_int_o;
|
||||
|
||||
wire [15:0] ss_pad_o;
|
||||
wire mosi_pad_o;
|
||||
wire miso_pad_i;
|
||||
|
||||
// There is a hold requirement of 10ns on the output path.
|
||||
// To ease meeting this requirement without to much routing added to the lines
|
||||
// these registers shift the output by 10ns (half 50 MHz period).
|
||||
always @(negedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
ss <= {8{1'b1}};
|
||||
mosi <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
ss <= ss_pad_o[LO_CHIP_SELECT_SIZE-1:0];
|
||||
mosi <= mosi_pad_o;
|
||||
end
|
||||
end
|
||||
|
||||
assign miso_pad_i = ( ~ss[TX0_LO1] ) ? miso[TX0_LO1] :
|
||||
( ~ss[TX0_LO2] ) ? miso[TX0_LO2] :
|
||||
( ~ss[TX1_LO1] ) ? miso[TX1_LO1] :
|
||||
( ~ss[TX1_LO2] ) ? miso[TX1_LO2] :
|
||||
( ~ss[RX0_LO1] ) ? miso[RX0_LO1] :
|
||||
( ~ss[RX0_LO2] ) ? miso[RX0_LO2] :
|
||||
( ~ss[RX1_LO1] ) ? miso[RX1_LO1] :
|
||||
( ~ss[RX1_LO2] ) ? miso[RX1_LO2] :
|
||||
1'b0;
|
||||
|
||||
// Import offsets and functions to interact with spi_top
|
||||
`include "utils/spi_control_utils.vh"
|
||||
|
||||
// The sclk signal generated by this spi engine will be constrained to be 1/4 of the
|
||||
// ctrl port frequency. The effective frequency of the clock output of spi_top is determined
|
||||
// by the equation wb_clk_i/((CLOCK_DIVIDER_VALUE+1)*2), so the value required for the clock
|
||||
// divider register is 1.
|
||||
localparam CLOCK_DIVIDER_VALUE = 32'h1;
|
||||
|
||||
// Base Configuration for the control register. To start a transaction
|
||||
// modify this value to include the GO_BUSY bit set to high. The mapping of the
|
||||
// macro goes as follows:
|
||||
`define CONTROL_DATA(GO_BUSY) { 18'b0, /* Reserved */ \
|
||||
1'b1, /* Automatic SS(13) */ \
|
||||
1'b1, /* Interrupt Enable */ \
|
||||
1'b0, /* LSB */ \
|
||||
1'b1, /* TX_NEG (10) */ \
|
||||
1'b0, /* RX_NEG (9) */ \
|
||||
GO_BUSY, /* GO_BUSY (8) */ \
|
||||
1'b0, /* Reserved (7) */ \
|
||||
7'd24} /* Length of spi transaction */
|
||||
|
||||
// Declare the different state-machine states.
|
||||
localparam RESET_STATE = 0;
|
||||
localparam CONFIG_DIVIDER = 1;
|
||||
localparam INIT_CONTROL = 2;
|
||||
localparam IDLE = 3;
|
||||
localparam LOAD_CS = 4;
|
||||
localparam LOAD_DATA = 5;
|
||||
localparam SEND_TRANSACTION = 6;
|
||||
localparam WAIT_FOR_COMPLETION = 7;
|
||||
localparam RETRIEVE_DATA = 8;
|
||||
|
||||
// FSM state variable
|
||||
reg [3:0] spi_state = RESET_STATE;
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
// SPI_STATUS for CtrlPort
|
||||
spi_state <= RESET_STATE;
|
||||
spi_ready <= 1'b1;
|
||||
spi_data_valid <= 1'b0;
|
||||
spi_rd_data <= {LO_SPI_RD_DATA_SIZE{1'b0}};
|
||||
|
||||
// SPI_TOP Bus access control.
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
wb_adr_i <= 5'h00;
|
||||
wb_dat_i <= 32'h00;
|
||||
end else begin
|
||||
case (spi_state)
|
||||
RESET_STATE:
|
||||
if (spi_start) begin
|
||||
spi_state <= CONFIG_DIVIDER;
|
||||
end
|
||||
|
||||
// keep driving a write to the CLOCK_DIVIDER Register until access is acknowledged.
|
||||
CONFIG_DIVIDER:
|
||||
if (wb_ack_o) begin
|
||||
spi_state <= INIT_CONTROL;
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end else begin
|
||||
wb_we_i <= 1'b1;
|
||||
wb_cyc_i <= 1'b1;
|
||||
wb_adr_i <= CLOCK_DIVIDER_REG; // CLOCK DIVIDER register offset
|
||||
wb_dat_i <= CLOCK_DIVIDER_VALUE;
|
||||
end
|
||||
|
||||
// keep driving a write to the CONTROL Register until access is acknowledged.
|
||||
INIT_CONTROL:
|
||||
if (wb_ack_o) begin
|
||||
spi_state <= LOAD_CS;
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end else begin
|
||||
wb_we_i <= 1'b1;
|
||||
wb_cyc_i <= 1'b1;
|
||||
wb_adr_i <= CONTROL_REG; //CONTROL register offset
|
||||
wb_dat_i <= `CONTROL_DATA(1'b0); //Write control register value with no GO_BUSY
|
||||
end
|
||||
|
||||
// Wait for CtrlPort operation to trigger a SPI transaction.
|
||||
IDLE :
|
||||
if (spi_start) begin
|
||||
spi_state <= LOAD_CS;
|
||||
spi_ready <= 1'b0;
|
||||
spi_data_valid <= 1'b0;
|
||||
// Clear data to be written next. This will make it so that the next state(LOAD_CS)
|
||||
// will only have to set the bits of the pertinent SS lines.
|
||||
wb_dat_i <= 32'h00;
|
||||
end else begin
|
||||
spi_ready <= 1'b1;
|
||||
wb_dat_i <= 32'h00;
|
||||
end
|
||||
|
||||
// keep driving a write to the SLAVE SELECT Register until access is acknowledged.
|
||||
LOAD_CS :
|
||||
if (wb_ack_o) begin
|
||||
spi_state <= LOAD_DATA;
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end else begin
|
||||
wb_we_i <= 1'b1;
|
||||
wb_cyc_i <= 1'b1;
|
||||
wb_adr_i <= SS_REG; // SS Register offset.
|
||||
wb_dat_i <= set_ss_bit(spi_cs); // Assign single bit.
|
||||
end
|
||||
|
||||
// keep driving a write to the DATA TRANSMIT Register until access is acknowledged.
|
||||
// This includes the combination of CMD+ADDR+DATA to be driven on the MOSI lines.
|
||||
LOAD_DATA :
|
||||
if (wb_ack_o) begin
|
||||
spi_state <= SEND_TRANSACTION;
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end else begin
|
||||
wb_we_i <= 1'b1;
|
||||
wb_cyc_i <= 1'b1;
|
||||
wb_adr_i <= TX_DATA_REG; // Data Transmit register offset.
|
||||
wb_dat_i <= {
|
||||
8'b0,
|
||||
spi_rd,
|
||||
spi_addr,
|
||||
spi_data
|
||||
};
|
||||
end
|
||||
|
||||
// Per indication in the SPI_TOP documentation, we write the same configuration as before to the
|
||||
// CONTROL register, with the addition of the GO bit.
|
||||
SEND_TRANSACTION :
|
||||
if (wb_ack_o) begin
|
||||
spi_state <= WAIT_FOR_COMPLETION;
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end else begin
|
||||
wb_we_i <= 1'b1;
|
||||
wb_cyc_i <= 1'b1;
|
||||
wb_adr_i <= CONTROL_REG;
|
||||
wb_dat_i <= `CONTROL_DATA(1'b1); //Write control register value with GO_BUSY set.
|
||||
end
|
||||
|
||||
// This state waits until SPI access is complete
|
||||
WAIT_FOR_COMPLETION:
|
||||
if (wb_int_o) begin
|
||||
if (spi_rd) begin // If reading, do an extra step
|
||||
spi_state <= RETRIEVE_DATA;
|
||||
end else begin
|
||||
spi_state <= IDLE; // If not reading, wait for next transaction
|
||||
end
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end else begin // Keep polling CONTROL register.
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end
|
||||
|
||||
RETRIEVE_DATA:
|
||||
if (wb_ack_o) begin
|
||||
spi_state <= IDLE; // as soon as data is available, record it and go back
|
||||
spi_rd_data <= wb_dat_o[LO_SPI_RD_DATA_SIZE-1:0]; // to idle.
|
||||
spi_data_valid <= 1'b1;
|
||||
wb_we_i <= 1'b0;
|
||||
wb_cyc_i <= 1'b0;
|
||||
end else begin
|
||||
wb_we_i <= 1'b0; // Drive bus access.
|
||||
wb_cyc_i <= 1'b1;
|
||||
wb_adr_i <= RX_DATA_REG; // DATA RETRIEVE Register offset
|
||||
wb_dat_i <= {LO_SPI_WT_DATA_SIZE{1'b0}};
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
spi_top spi_top_i (
|
||||
.wb_clk_i (ctrlport_clk),
|
||||
.wb_rst_i (ctrlport_rst),
|
||||
.wb_adr_i (wb_adr_i),
|
||||
.wb_dat_i (wb_dat_i),
|
||||
.wb_dat_o (wb_dat_o),
|
||||
.wb_sel_i (4'hF),
|
||||
.wb_we_i (wb_we_i),
|
||||
.wb_stb_i (wb_cyc_i),
|
||||
.wb_cyc_i (wb_cyc_i),
|
||||
.wb_ack_o (wb_ack_o),
|
||||
.wb_err_o (),
|
||||
.wb_int_o (wb_int_o),
|
||||
.ss_pad_o (ss_pad_o),
|
||||
.sclk_pad_o (sclk),
|
||||
.mosi_pad_o (mosi_pad_o),
|
||||
.miso_pad_i (miso_pad_i));
|
||||
|
||||
reg mb_sync_reg = 1'b0;
|
||||
|
||||
// align incoming signal to clock
|
||||
always @(posedge ctrlport_clk) begin
|
||||
mb_sync_reg <= mb_synth_sync;
|
||||
end
|
||||
|
||||
// Select between bypassing into input signal or registered pulse
|
||||
assign tx0_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX0_LO1];
|
||||
assign tx0_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX0_LO2];
|
||||
assign tx1_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX1_LO1];
|
||||
assign tx1_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[TX1_LO2];
|
||||
assign rx0_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX0_LO1];
|
||||
assign rx0_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX0_LO2];
|
||||
assign rx1_lo1_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX1_LO1];
|
||||
assign rx1_lo2_sync = bypass_sync ? mb_sync_reg : lo_sync_reg[RX1_LO2];
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="LO_CONTROL_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
||||
// <group name="LO_SPI_REGISTERS">
|
||||
// <info>
|
||||
// Controls the SPI transaction to the LMX2572
|
||||
// </info>
|
||||
// <enumeratedtype name="LO_CHIP_SELECT">
|
||||
// <value name="TX0_LO1" integer="0"/>
|
||||
// <value name="TX0_LO2" integer="1"/>
|
||||
// <value name="TX1_LO1" integer="2"/>
|
||||
// <value name="TX1_LO2" integer="3"/>
|
||||
// <value name="RX0_LO1" integer="4"/>
|
||||
// <value name="RX0_LO2" integer="5"/>
|
||||
// <value name="RX1_LO1" integer="6"/>
|
||||
// <value name="RX1_LO2" integer="7"/>
|
||||
// </enumeratedtype>
|
||||
// <register name="LO_SPI_SETUP" size="32" offset="0x00" attributes="Writable">
|
||||
// <info>
|
||||
// This register sets up the SPI transaction to read/write to/from to the LMX2572.
|
||||
// </info>
|
||||
// <bitfield name="LO_SPI_START_TRANSACTION" range="28" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Strobe this bit high to start the SPI transaction with the bitfields below
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SELECT" range="26..24" type="LO_CHIP_SELECT" initialvalue="TX0_LO1" attributes="Strobe">
|
||||
// <info>
|
||||
// Sets the CS to the selected LO. The CS will assert until after @.LO_SPI_START_TRANSACTION has been asserted.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SPI_RD" range="23" initialvalue="0">
|
||||
// <info>
|
||||
// Set this bit to '1' to read from the LMX2572. Set this bit to '0' to write to the LMX2572.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SPI_WT_ADDR" range="22..16" initialvalue="0">
|
||||
// <info>
|
||||
// 7 bit address of the LMX2572
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SPI_WT_DATA" range="15..0" initialvalue="0">
|
||||
// <info>
|
||||
// Write Data to the LMX2572
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
//
|
||||
// <register name="LO_SPI_STATUS" size="32" offset="0x00" attributes="Readable">
|
||||
// <info>
|
||||
// This register returns the SPI master status, and also returns the read data from the LMX2572
|
||||
// </info>
|
||||
// <bitfield name="LO_SPI_DATA_VALID" range="31" initialvalue="0">
|
||||
// <info>
|
||||
// Returns '1' when a read SPI transaction is complete. This bit will remain high until a new SPI transaction has started.
|
||||
// i.e. @.LO_SPI_START_TRANSACTION is strobed. Poll this when expecting data from a read transaction.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SPI_READY" range="30" initialvalue="0">
|
||||
// <info>
|
||||
// If this bit returns '1' then LMX2572 is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction.
|
||||
// Poll this bit before starting a SPI transaction.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SELECT_STATUS" range="26..24" type="LO_CHIP_SELECT" initialvalue="TX0_LO1">
|
||||
// <info>
|
||||
// Returns the current selected CS. This bitfield will return the value written to @.LO_SELECT bitfield in the @.LO_SPI_SETUP reg.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SPI_RD_ADDR" range="22..16" initialvalue="0">
|
||||
// <info>
|
||||
// Returns the address of the current SPI address setup
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="LO_SPI_RD_DATA" range="15..0" initialvalue="0">
|
||||
// <info>
|
||||
// Returns the data of the SPI read. This bitfield will return 0x0000 until @.LO_SPI_DATA_VALID is true. This bit field will maintain it's
|
||||
// read value until a new SPI transaction has started. i.e. @.LO_SPI_START_TRANSACTION is strobed.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// </group>
|
||||
// <group name="LO_SYNC_REGS" offset="0x04">
|
||||
// <info>
|
||||
// Contains registers that control the logic lines in charge of synchronization
|
||||
// </info>
|
||||
// <register name="LO_PULSE_SYNC" size="32" offset="0x00" attributes="Writable">
|
||||
// <info>
|
||||
// Controls pulses driven to the SYNC pins of the LMX2572 chips
|
||||
// </info>
|
||||
// <bitfield name="PULSE_TX0_LO1_SYNC" range="0" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the TX0_LO1_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PULSE_TX0_LO2_SYNC" range="1" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the TX0_LO2_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PULSE_TX1_LO1_SYNC" range="2" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the TX1_LO1_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PULSE_TX1_LO2_SYNC" range="3" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the TX1_LO2_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PULSE_RX0_LO1_SYNC" range="4" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the RX0_LO1_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PULSE_RX0_LO2_SYNC" range="5" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the RX0_LO2_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PULSE_RX1_LO1_SYNC" range="6" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the RX1_LO1_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="PULSE_RX1_LO2_SYNC" range="7" initialvalue="0" attributes="Strobe">
|
||||
// <info>
|
||||
// Creates a single cycle pulse on the RX1_LO2_SYNC line.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="BYPASS_SYNC_REGISTER" range="8" initialvalue="0">
|
||||
// <info>
|
||||
// Setting this bit to '1' will ignore writes to the PULSE_X_SYNC fields and allow
|
||||
// a buffered input SYNC pulse to be driven out instead.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,2 @@
|
||||
zbx_cpld_regs_t.py
|
||||
*.hex
|
||||
@@ -0,0 +1,65 @@
|
||||
#!/usr/bin/env python3
|
||||
#
|
||||
# Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#
|
||||
"""
|
||||
Helper script to generate memory init files for the ZBX CPLD.
|
||||
"""
|
||||
|
||||
import os
|
||||
import pathlib
|
||||
|
||||
# This is generated by running
|
||||
# $ python3 /path/to/gen_zbx_cpld_regs.py zbx_cpld_regs_t.py
|
||||
import zbx_cpld_regs_t
|
||||
|
||||
def main():
|
||||
"""
|
||||
Main function
|
||||
"""
|
||||
cur_dir = str(pathlib.Path(__file__).resolve().parent)
|
||||
|
||||
zbx_regs = zbx_cpld_regs_t.zbx_cpld_regs_t()
|
||||
|
||||
# The file dsa_control.v lists default values for documentation purposes. When
|
||||
# changing these values, make sure to also update the 'initialvalue' documentation
|
||||
# attributes in dsa_control.v
|
||||
zbx_regs.TX0_DSA1[0] = 31
|
||||
zbx_regs.TX0_DSA2[0] = 31
|
||||
|
||||
zbx_regs.RX0_DSA1[0] = 15
|
||||
zbx_regs.RX0_DSA2[0] = 15
|
||||
zbx_regs.RX0_DSA3_A[0] = 15
|
||||
zbx_regs.RX0_DSA3_B[0] = 15
|
||||
|
||||
# Path control defaults
|
||||
with open(os.path.join(cur_dir, "tx0_path_defaults.hex"), "w") as outfile:
|
||||
outfile.write("\n".join([
|
||||
"{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('TX0_IF2_1_2'))),
|
||||
] * len(zbx_regs.TX0_IF2_1_2)))
|
||||
with open(os.path.join(cur_dir, "tx1_path_defaults.hex"), "w") as outfile:
|
||||
outfile.write("\n".join([
|
||||
"{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('TX1_IF2_1_2'))),
|
||||
] * len(zbx_regs.TX1_IF2_1_2)))
|
||||
with open(os.path.join(cur_dir, "rx0_path_defaults.hex"), "w") as outfile:
|
||||
outfile.write("\n".join([
|
||||
"{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('RX0_ANT_1'))),
|
||||
] * len(zbx_regs.RX0_ANT_1)))
|
||||
with open(os.path.join(cur_dir, "rx1_path_defaults.hex"), "w") as outfile:
|
||||
outfile.write("\n".join([
|
||||
"{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('RX1_ANT_1'))),
|
||||
] * len(zbx_regs.RX1_ANT_1)))
|
||||
# DSA defaults
|
||||
with open(os.path.join(cur_dir, "tx_dsa_defaults.hex"), "w") as outfile:
|
||||
outfile.write("\n".join([
|
||||
"{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('TX0_DSA1'))),
|
||||
] * len(zbx_regs.TX0_DSA1)))
|
||||
with open(os.path.join(cur_dir, "rx_dsa_defaults.hex"), "w") as outfile:
|
||||
outfile.write("\n".join([
|
||||
"{:08X}".format(zbx_regs.get_reg(zbx_regs.get_addr('RX0_DSA1'))),
|
||||
] * len(zbx_regs.RX0_DSA1)))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@@ -0,0 +1,211 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: power_regs
|
||||
//
|
||||
// Description:
|
||||
// Registers to control the power supplies and the PLL ref clock buffer.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module power_regs #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
// Response
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output reg [ 1:0] s_ctrlport_resp_status,
|
||||
output reg [31:0] s_ctrlport_resp_data,
|
||||
|
||||
//reg clk domain
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
//Power Control
|
||||
output wire enable_tx_7v0,
|
||||
output wire enable_rx_7v0,
|
||||
output wire enable_3v3,
|
||||
|
||||
//Power Good Indicators
|
||||
input wire p7v_pg_b,
|
||||
input wire p7v_pg_a,
|
||||
|
||||
//PRC buffer
|
||||
output reg pll_ref_clk_enable = 1'b0
|
||||
);
|
||||
|
||||
`include "../regmap/power_regs_regmap_utils.vh"
|
||||
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Internal registers
|
||||
//----------------------------------------------------------
|
||||
reg enable_3v3_reg = {ENABLE_3V3_SIZE {1'b0}};
|
||||
reg enable_rx_7v0_reg = {ENABLE_RX_7V0_SIZE {1'b0}};
|
||||
reg enable_tx_7v0_reg = {ENABLE_TX_7V0_SIZE {1'b0}};
|
||||
|
||||
//----------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//----------------------------------------------------------
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// reset internal registers and responses
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
enable_3v3_reg <= {ENABLE_3V3_SIZE {1'b0}};
|
||||
enable_rx_7v0_reg <= {ENABLE_RX_7V0_SIZE {1'b0}};
|
||||
enable_tx_7v0_reg <= {ENABLE_TX_7V0_SIZE {1'b0}};
|
||||
|
||||
end else begin
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport_req_wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + RF_POWER_CONTROL: begin
|
||||
enable_3v3_reg <= s_ctrlport_req_data[ENABLE_3V3];
|
||||
enable_rx_7v0_reg <= s_ctrlport_req_data[ENABLE_RX_7V0];
|
||||
enable_tx_7v0_reg <= s_ctrlport_req_data[ENABLE_TX_7V0];
|
||||
end
|
||||
|
||||
BASE_ADDRESS + PRC_CONTROL: begin
|
||||
pll_ref_clk_enable <= s_ctrlport_req_data[PLL_REF_CLOCK_ENABLE];
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// read requests
|
||||
end else if (s_ctrlport_req_rd) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
|
||||
case (s_ctrlport_req_addr)
|
||||
BASE_ADDRESS + RF_POWER_CONTROL: begin
|
||||
s_ctrlport_resp_data[ENABLE_3V3] <= enable_3v3_reg;
|
||||
s_ctrlport_resp_data[ENABLE_RX_7V0] <= enable_rx_7v0_reg;
|
||||
s_ctrlport_resp_data[ENABLE_TX_7V0] <= enable_tx_7v0_reg;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + RF_POWER_STATUS: begin
|
||||
s_ctrlport_resp_data[P7V_A_STATUS] <= p7v_pg_a;
|
||||
s_ctrlport_resp_data[P7V_B_STATUS] <= p7v_pg_b;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + PRC_CONTROL: begin
|
||||
s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLE] <= pll_ref_clk_enable;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign enable_tx_7v0 = enable_tx_7v0_reg;
|
||||
assign enable_rx_7v0 = enable_rx_7v0_reg;
|
||||
assign enable_3v3 = enable_3v3_reg;
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="POWER_REGS_REGMAP" generatevhdl="true" ettusguidelines="true">
|
||||
// <group name="POWER_REGS_REGISTERS" size="0x010">
|
||||
// <info>
|
||||
// This regmap contains the registers to control the power supplies and the clock buffer for PLL reference clock.
|
||||
// </info>
|
||||
// <register name="RF_POWER_CONTROL" size="32" offset="0x00" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// This register controls power supply enables to the Tx/Rx amps, switch control, and clk buffers. During normal
|
||||
// operations, all three power supplies should be enabled.
|
||||
// </info>
|
||||
// <bitfield name="ENABLE_3v3" range="2" initialvalue="0">
|
||||
// <info>
|
||||
// This power supply sources the switch control, and the clock buffers. By default this power supply is off.
|
||||
// The internal LOs will not work unless this bit is enabled.{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_RX_7V0" range="1" initialvalue="0">
|
||||
// <info>
|
||||
// This power supply sources the Rx0 and Rx1 amps. By default this power supply is off.The Rx0/1 path will not
|
||||
// be active unless this power supply is enabled. Disabling this bit is similar to RX RF blanking{BR/}
|
||||
// {font color="red"}note to digital engineer, this is Pos7v0B{/font}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="ENABLE_TX_7V0" range="0" initialvalue="0">
|
||||
// <info>
|
||||
// This power supply sources the Tx0 and Tx1 amps. By default this power supply is off. The Tx0/1 path will not
|
||||
// be active unless this power supply is enabled. Disabling this bit is similar to TX RF blanking{BR/}
|
||||
// {font color="red"}note to digital engineer, this is Pos7v0A{/font}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="RF_POWER_STATUS" size="32" offset="0x04" attributes="Readable">
|
||||
// <info>
|
||||
// Returns status of PowerGood indicators across the daughterboard.
|
||||
// </info>
|
||||
// <bitfield name="P7V_A_STATUS" range="0">
|
||||
// <info>
|
||||
// Returns status of 7V switching regulator A.{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="P7V_B_STATUS" range="1">
|
||||
// <info>
|
||||
// Returns status of 7V switching regulator B.{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// <register name="PRC_CONTROL" size="32" offset="0x08" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// Offers ability to enable or disable the PLL reference clock.
|
||||
// </info>
|
||||
// <bitfield name="PLL_REF_CLOCK_ENABLE" range="0" initialvalue="0">
|
||||
// <info>If set PLL reference clock is enabled.</info>
|
||||
// </bitfield>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,918 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: switch_control
|
||||
//
|
||||
// Description:
|
||||
// Implements control over RF switches via CtrlPort. Uses RAM to store multiple
|
||||
// ATR configurations.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module switch_control #(
|
||||
parameter [19:0] BASE_ADDRESS = 0,
|
||||
parameter [19:0] SIZE_ADDRESS = 0
|
||||
) (
|
||||
// Clock and reset
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
|
||||
// Response
|
||||
output reg s_ctrlport_resp_ack,
|
||||
output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
|
||||
output reg [31:0] s_ctrlport_resp_data = 32'b0,
|
||||
|
||||
// ATR switching
|
||||
input wire [ 7:0] atr_config_rf0,
|
||||
input wire [ 7:0] atr_config_rf1,
|
||||
|
||||
//Tx0 Switch control (domain: ctrl_reg_clk)
|
||||
output wire tx0_sw1_sw2_ctrl,
|
||||
output wire tx0_sw3_a,
|
||||
output wire tx0_sw3_b,
|
||||
output wire tx0_sw4_a,
|
||||
output wire tx0_sw4_b,
|
||||
output wire tx0_sw5_a,
|
||||
output wire tx0_sw5_b,
|
||||
output wire tx0_sw6_a,
|
||||
output wire tx0_sw6_b,
|
||||
output wire tx0_sw7_a,
|
||||
output wire tx0_sw7_b,
|
||||
output wire tx0_sw8_v1,
|
||||
output wire tx0_sw8_v2,
|
||||
output wire tx0_sw8_v3,
|
||||
output wire tx0_sw9_a,
|
||||
output wire tx0_sw9_b,
|
||||
output wire tx0_sw10_a,
|
||||
output wire tx0_sw10_b,
|
||||
output wire tx0_sw11_a,
|
||||
output wire tx0_sw11_b,
|
||||
output wire tx0_sw13_v1,
|
||||
output wire tx0_sw14_v1,
|
||||
|
||||
//Tx1 Switch control (domain: ctrl_reg_clk)
|
||||
output wire tx1_sw1_sw2_ctrl,
|
||||
output wire tx1_sw3_a,
|
||||
output wire tx1_sw3_b,
|
||||
output wire tx1_sw4_a,
|
||||
output wire tx1_sw4_b,
|
||||
output wire tx1_sw5_a,
|
||||
output wire tx1_sw5_b,
|
||||
output wire tx1_sw6_a,
|
||||
output wire tx1_sw6_b,
|
||||
output wire tx1_sw7_a,
|
||||
output wire tx1_sw7_b,
|
||||
output wire tx1_sw8_v1,
|
||||
output wire tx1_sw8_v2,
|
||||
output wire tx1_sw8_v3,
|
||||
output wire tx1_sw9_a,
|
||||
output wire tx1_sw9_b,
|
||||
output wire tx1_sw10_a,
|
||||
output wire tx1_sw10_b,
|
||||
output wire tx1_sw11_a,
|
||||
output wire tx1_sw11_b,
|
||||
output wire tx1_sw13_v1,
|
||||
output wire tx1_sw14_v1,
|
||||
|
||||
//Rx0 Switch control (domain: ctrl_reg_clk)
|
||||
output wire rx0_sw1_a,
|
||||
output wire rx0_sw1_b,
|
||||
output wire rx0_sw2_a,
|
||||
output wire rx0_sw3_v1,
|
||||
output wire rx0_sw3_v2,
|
||||
output wire rx0_sw3_v3,
|
||||
output wire rx0_sw4_a,
|
||||
output wire rx0_sw5_a,
|
||||
output wire rx0_sw5_b,
|
||||
output wire rx0_sw6_a,
|
||||
output wire rx0_sw6_b,
|
||||
output wire rx0_sw7_sw8_ctrl,
|
||||
output wire rx0_sw9_v1,
|
||||
output wire rx0_sw10_v1,
|
||||
output wire rx0_sw11_v3,
|
||||
output wire rx0_sw11_v2,
|
||||
output wire rx0_sw11_v1,
|
||||
|
||||
//Rx1 Switch control (domain: ctrl_reg_clk)
|
||||
output wire rx1_sw1_a,
|
||||
output wire rx1_sw1_b,
|
||||
output wire rx1_sw2_a,
|
||||
output wire rx1_sw3_v1,
|
||||
output wire rx1_sw3_v2,
|
||||
output wire rx1_sw3_v3,
|
||||
output wire rx1_sw4_a,
|
||||
output wire rx1_sw5_a,
|
||||
output wire rx1_sw5_b,
|
||||
output wire rx1_sw6_a,
|
||||
output wire rx1_sw6_b,
|
||||
output wire rx1_sw7_sw8_ctrl,
|
||||
output wire rx1_sw9_v1,
|
||||
output wire rx1_sw10_v1,
|
||||
output wire rx1_sw11_v3,
|
||||
output wire rx1_sw11_v2,
|
||||
output wire rx1_sw11_v1
|
||||
);
|
||||
|
||||
`include "../regmap/switch_setup_regmap_utils.vh"
|
||||
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// register bitfields
|
||||
//---------------------------------------------------------------
|
||||
//Tx0PathControl Register
|
||||
reg [ TX_SWITCH_1_2_SIZE-1:0] tx0_switch_1_2_reg;
|
||||
reg [ TX_SWITCH_3_SIZE-1:0] tx0_switch_3_reg;
|
||||
reg [ TX_SWITCH_4_SIZE-1:0] tx0_switch_4_reg;
|
||||
reg [ TX_SWITCH_5_SIZE-1:0] tx0_switch_5_reg;
|
||||
reg [ TX_SWITCH_6_SIZE-1:0] tx0_switch_6_reg;
|
||||
reg [ TX_SWITCH_7_SIZE-1:0] tx0_switch_7_reg;
|
||||
reg [ TX_SWITCH_8_SIZE-1:0] tx0_switch_8_reg;
|
||||
reg [ TX_SWITCH_9_SIZE-1:0] tx0_switch_9_reg;
|
||||
reg [ TX_SWITCH_10_SIZE-1:0] tx0_switch_10_reg;
|
||||
reg [ TX_SWITCH_11_SIZE-1:0] tx0_switch_11_reg;
|
||||
reg [ TX_SWITCH_13_SIZE-1:0] tx0_switch_13_reg;
|
||||
reg [ TX_SWITCH_14_SIZE-1:0] tx0_switch_14_reg;
|
||||
|
||||
//Tx1PathControl Register
|
||||
reg [ TX_SWITCH_1_2_SIZE-1:0] tx1_switch_1_2_reg;
|
||||
reg [ TX_SWITCH_3_SIZE-1:0] tx1_switch_3_reg;
|
||||
reg [ TX_SWITCH_4_SIZE-1:0] tx1_switch_4_reg;
|
||||
reg [ TX_SWITCH_5_SIZE-1:0] tx1_switch_5_reg;
|
||||
reg [ TX_SWITCH_6_SIZE-1:0] tx1_switch_6_reg;
|
||||
reg [ TX_SWITCH_7_SIZE-1:0] tx1_switch_7_reg;
|
||||
reg [ TX_SWITCH_8_SIZE-1:0] tx1_switch_8_reg;
|
||||
reg [ TX_SWITCH_9_SIZE-1:0] tx1_switch_9_reg;
|
||||
reg [ TX_SWITCH_10_SIZE-1:0] tx1_switch_10_reg;
|
||||
reg [ TX_SWITCH_11_SIZE-1:0] tx1_switch_11_reg;
|
||||
reg [ TX_SWITCH_13_SIZE-1:0] tx1_switch_13_reg;
|
||||
reg [ TX_SWITCH_14_SIZE-1:0] tx1_switch_14_reg;
|
||||
|
||||
//Rx0PathControl Register
|
||||
reg [ RX_SWITCH_1_SIZE-1:0] rx0_switch_1_reg;
|
||||
reg [ RX_SWITCH_2_SIZE-1:0] rx0_switch_2_reg;
|
||||
reg [ RX_SWITCH_3_SIZE-1:0] rx0_switch_3_reg;
|
||||
reg [ RX_SWITCH_4_SIZE-1:0] rx0_switch_4_reg;
|
||||
reg [ RX_SWITCH_5_SIZE-1:0] rx0_switch_5_reg;
|
||||
reg [ RX_SWITCH_6_SIZE-1:0] rx0_switch_6_reg;
|
||||
reg [ RX_SWITCH_7_8_SIZE-1:0] rx0_switch_7_8_reg;
|
||||
reg [ RX_SWITCH_9_SIZE-1:0] rx0_switch_9_reg;
|
||||
reg [ RX_SWITCH_10_SIZE-1:0] rx0_switch_10_reg;
|
||||
reg [ RX_SWITCH_11_SIZE-1:0] rx0_switch_11_reg;
|
||||
|
||||
//Rx1PathControl Register
|
||||
reg [ RX_SWITCH_1_SIZE-1:0] rx1_switch_1_reg;
|
||||
reg [ RX_SWITCH_2_SIZE-1:0] rx1_switch_2_reg;
|
||||
reg [ RX_SWITCH_3_SIZE-1:0] rx1_switch_3_reg;
|
||||
reg [ RX_SWITCH_4_SIZE-1:0] rx1_switch_4_reg;
|
||||
reg [ RX_SWITCH_5_SIZE-1:0] rx1_switch_5_reg;
|
||||
reg [ RX_SWITCH_6_SIZE-1:0] rx1_switch_6_reg;
|
||||
reg [ RX_SWITCH_7_8_SIZE-1:0] rx1_switch_7_8_reg;
|
||||
reg [ RX_SWITCH_9_SIZE-1:0] rx1_switch_9_reg;
|
||||
reg [ RX_SWITCH_10_SIZE-1:0] rx1_switch_10_reg;
|
||||
reg [ RX_SWITCH_11_SIZE-1:0] rx1_switch_11_reg;
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// ATR memory signals
|
||||
//---------------------------------------------------------------
|
||||
reg ram_rx0_wea;
|
||||
wire [31:0] ram_rx0_doa;
|
||||
wire [31:0] ram_rx0_dob;
|
||||
|
||||
reg ram_rx1_wea;
|
||||
wire [31:0] ram_rx1_doa;
|
||||
wire [31:0] ram_rx1_dob;
|
||||
|
||||
reg ram_tx0_wea;
|
||||
wire [31:0] ram_tx0_doa;
|
||||
wire [31:0] ram_tx0_dob;
|
||||
|
||||
reg ram_tx1_wea;
|
||||
wire [31:0] ram_tx1_doa;
|
||||
wire [31:0] ram_tx1_dob;
|
||||
|
||||
|
||||
//---------------------------------------------------------------
|
||||
// Handling of CtrlPort
|
||||
//---------------------------------------------------------------
|
||||
// Check of request address is targeted for this module.
|
||||
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
|
||||
// Read request shift register to align memory read and response generation.
|
||||
reg [ 1:0] read_req_shift_reg = 2'b0;
|
||||
// Mask out 8 bits for ATR configurations to be able to compare all ATR
|
||||
// configurations against the same base register address.
|
||||
wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};
|
||||
// Extract masked out bits from the address, which represent the register
|
||||
// array index = ATR configuration index
|
||||
wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];
|
||||
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// reset internal registers and responses
|
||||
if (ctrlport_rst) begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
|
||||
read_req_shift_reg <= 2'b0;
|
||||
|
||||
ram_tx0_wea <= 1'b0;
|
||||
ram_tx1_wea <= 1'b0;
|
||||
ram_rx0_wea <= 1'b0;
|
||||
ram_rx1_wea <= 1'b0;
|
||||
|
||||
end else begin
|
||||
// default assignments
|
||||
read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};
|
||||
|
||||
ram_tx0_wea <= 1'b0;
|
||||
ram_tx1_wea <= 1'b0;
|
||||
ram_rx0_wea <= 1'b0;
|
||||
ram_rx1_wea <= 1'b0;
|
||||
|
||||
// write requests
|
||||
if (s_ctrlport_req_wr) begin
|
||||
// always issue an ack and no data
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_data <= {32{1'bx}};
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
|
||||
case (register_base_address)
|
||||
BASE_ADDRESS + TX0_PATH_CONTROL(0): begin
|
||||
ram_tx0_wea <= 1'b1;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + TX1_PATH_CONTROL(0): begin
|
||||
ram_tx1_wea <= 1'b1;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + RX0_PATH_CONTROL(0): begin
|
||||
ram_rx0_wea <= 1'b1;
|
||||
end
|
||||
|
||||
BASE_ADDRESS + RX1_PATH_CONTROL(0): begin
|
||||
ram_rx1_wea <= 1'b1;
|
||||
end
|
||||
|
||||
// error on undefined address
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// Answer read requests delayed by 2 clock cycles. This compensated for
|
||||
// register ram_addr and the memory internal address register to make sure
|
||||
// ram_ch0_doa is up to date when generating the response.
|
||||
end else if (read_req_shift_reg[1]) begin
|
||||
// default assumption: valid request
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
s_ctrlport_resp_data <= {32{1'b0}};
|
||||
|
||||
case (register_base_address)
|
||||
BASE_ADDRESS + TX0_PATH_CONTROL(0): begin
|
||||
s_ctrlport_resp_data <= ram_tx0_doa & TX_PATH_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + TX1_PATH_CONTROL(0): begin
|
||||
s_ctrlport_resp_data <= ram_tx1_doa & TX_PATH_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + RX0_PATH_CONTROL(0): begin
|
||||
s_ctrlport_resp_data <= ram_rx0_doa & RX_PATH_CONTROL_MASK;
|
||||
end
|
||||
BASE_ADDRESS + RX1_PATH_CONTROL(0): begin
|
||||
s_ctrlport_resp_data <= ram_rx1_doa & RX_PATH_CONTROL_MASK;
|
||||
end
|
||||
|
||||
default: begin
|
||||
if (address_in_range) begin
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// no response if out of range
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
|
||||
// no request
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// register without reset
|
||||
reg [ 7:0] ram_addr = 8'b0;
|
||||
reg [31:0] ram_datain = 32'b0;
|
||||
always @(posedge ctrlport_clk) begin
|
||||
// memories
|
||||
ram_addr <= register_index;
|
||||
ram_datain <= s_ctrlport_req_data;
|
||||
|
||||
// outputs
|
||||
tx0_switch_1_2_reg <= ram_tx0_dob[TX_SWITCH_1_2];
|
||||
tx0_switch_3_reg <= ram_tx0_dob[TX_SWITCH_3_MSB : TX_SWITCH_3];
|
||||
tx0_switch_4_reg <= ram_tx0_dob[TX_SWITCH_4_MSB : TX_SWITCH_4];
|
||||
tx0_switch_5_reg <= ram_tx0_dob[TX_SWITCH_5_MSB : TX_SWITCH_5];
|
||||
tx0_switch_6_reg <= ram_tx0_dob[TX_SWITCH_6_MSB : TX_SWITCH_6];
|
||||
tx0_switch_7_reg <= ram_tx0_dob[TX_SWITCH_7_MSB : TX_SWITCH_7];
|
||||
tx0_switch_8_reg <= ram_tx0_dob[TX_SWITCH_8_MSB : TX_SWITCH_8];
|
||||
tx0_switch_9_reg <= ram_tx0_dob[TX_SWITCH_9_MSB : TX_SWITCH_9];
|
||||
tx0_switch_10_reg <= ram_tx0_dob[TX_SWITCH_10_MSB : TX_SWITCH_10];
|
||||
tx0_switch_11_reg <= ram_tx0_dob[TX_SWITCH_11_MSB : TX_SWITCH_11];
|
||||
tx0_switch_13_reg <= ram_tx0_dob[TX_SWITCH_13];
|
||||
tx0_switch_14_reg <= ram_tx0_dob[TX_SWITCH_14];
|
||||
|
||||
tx1_switch_1_2_reg <= ram_tx1_dob[TX_SWITCH_1_2];
|
||||
tx1_switch_3_reg <= ram_tx1_dob[TX_SWITCH_3_MSB : TX_SWITCH_3];
|
||||
tx1_switch_4_reg <= ram_tx1_dob[TX_SWITCH_4_MSB : TX_SWITCH_4];
|
||||
tx1_switch_5_reg <= ram_tx1_dob[TX_SWITCH_5_MSB : TX_SWITCH_5];
|
||||
tx1_switch_6_reg <= ram_tx1_dob[TX_SWITCH_6_MSB : TX_SWITCH_6];
|
||||
tx1_switch_7_reg <= ram_tx1_dob[TX_SWITCH_7_MSB : TX_SWITCH_7];
|
||||
tx1_switch_8_reg <= ram_tx1_dob[TX_SWITCH_8_MSB : TX_SWITCH_8];
|
||||
tx1_switch_9_reg <= ram_tx1_dob[TX_SWITCH_9_MSB : TX_SWITCH_9];
|
||||
tx1_switch_10_reg <= ram_tx1_dob[TX_SWITCH_10_MSB : TX_SWITCH_10];
|
||||
tx1_switch_11_reg <= ram_tx1_dob[TX_SWITCH_11_MSB : TX_SWITCH_11];
|
||||
tx1_switch_13_reg <= ram_tx1_dob[TX_SWITCH_13];
|
||||
tx1_switch_14_reg <= ram_tx1_dob[TX_SWITCH_14];
|
||||
|
||||
rx0_switch_1_reg <= ram_rx0_dob[RX_SWITCH_1_MSB : RX_SWITCH_1];
|
||||
rx0_switch_2_reg <= ram_rx0_dob[RX_SWITCH_2];
|
||||
rx0_switch_3_reg <= ram_rx0_dob[RX_SWITCH_3_MSB : RX_SWITCH_3];
|
||||
rx0_switch_4_reg <= ram_rx0_dob[RX_SWITCH_4];
|
||||
rx0_switch_5_reg <= ram_rx0_dob[RX_SWITCH_5_MSB : RX_SWITCH_5];
|
||||
rx0_switch_6_reg <= ram_rx0_dob[RX_SWITCH_6_MSB : RX_SWITCH_6];
|
||||
rx0_switch_7_8_reg <= ram_rx0_dob[RX_SWITCH_7_8];
|
||||
rx0_switch_9_reg <= ram_rx0_dob[RX_SWITCH_9];
|
||||
rx0_switch_10_reg <= ram_rx0_dob[RX_SWITCH_10];
|
||||
rx0_switch_11_reg <= ram_rx0_dob[RX_SWITCH_11_MSB: RX_SWITCH_11];
|
||||
|
||||
rx1_switch_1_reg <= ram_rx1_dob[RX_SWITCH_1_MSB : RX_SWITCH_1];
|
||||
rx1_switch_2_reg <= ram_rx1_dob[RX_SWITCH_2];
|
||||
rx1_switch_3_reg <= ram_rx1_dob[RX_SWITCH_3_MSB : RX_SWITCH_3];
|
||||
rx1_switch_4_reg <= ram_rx1_dob[RX_SWITCH_4];
|
||||
rx1_switch_5_reg <= ram_rx1_dob[RX_SWITCH_5_MSB : RX_SWITCH_5];
|
||||
rx1_switch_6_reg <= ram_rx1_dob[RX_SWITCH_6_MSB : RX_SWITCH_6];
|
||||
rx1_switch_7_8_reg <= ram_rx1_dob[RX_SWITCH_7_8];
|
||||
rx1_switch_9_reg <= ram_rx1_dob[RX_SWITCH_9];
|
||||
rx1_switch_10_reg <= ram_rx1_dob[RX_SWITCH_10];
|
||||
rx1_switch_11_reg <= ram_rx1_dob[RX_SWITCH_11_MSB: RX_SWITCH_11];
|
||||
end
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/tx0_path_defaults.hex")
|
||||
) ram_tx0_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_tx0_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (ram_tx0_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf0),
|
||||
.dib (0),
|
||||
.dob (ram_tx0_dob));
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/tx1_path_defaults.hex")
|
||||
) ram_tx1_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_tx1_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (ram_tx1_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf1),
|
||||
.dib (0),
|
||||
.dob (ram_tx1_dob));
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/rx0_path_defaults.hex")
|
||||
) ram_rx0_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_rx0_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (ram_rx0_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf0),
|
||||
.dib (0),
|
||||
.dob (ram_rx0_dob));
|
||||
|
||||
ram_2port #(
|
||||
.DWIDTH (32),
|
||||
.AWIDTH (8),
|
||||
.RW_MODE ("READ-FIRST"),
|
||||
.RAM_TYPE ("AUTOMATIC"),
|
||||
.OUT_REG (0),
|
||||
.INIT_FILE ("register_endpoints/memory_init_files/rx1_path_defaults.hex")
|
||||
) ram_rx1_i (
|
||||
.clka (ctrlport_clk),
|
||||
.ena (1'b1),
|
||||
.wea (ram_rx1_wea),
|
||||
.addra (ram_addr),
|
||||
.dia (ram_datain),
|
||||
.doa (ram_rx1_doa),
|
||||
.clkb (ctrlport_clk),
|
||||
.enb (1'b1),
|
||||
.web (1'b0),
|
||||
.addrb (atr_config_rf1),
|
||||
.dib (0),
|
||||
.dob (ram_rx1_dob));
|
||||
|
||||
assign tx0_sw1_sw2_ctrl = tx0_switch_1_2_reg;
|
||||
assign tx0_sw3_a = tx0_switch_3_reg[0];
|
||||
assign tx0_sw3_b = tx0_switch_3_reg[1];
|
||||
assign tx0_sw4_a = tx0_switch_4_reg[0];
|
||||
assign tx0_sw4_b = tx0_switch_4_reg[1];
|
||||
assign tx0_sw5_a = tx0_switch_5_reg[0];
|
||||
assign tx0_sw5_b = tx0_switch_5_reg[1];
|
||||
assign tx0_sw6_a = tx0_switch_6_reg[0];
|
||||
assign tx0_sw6_b = tx0_switch_6_reg[1];
|
||||
assign tx0_sw7_a = tx0_switch_7_reg[0];
|
||||
assign tx0_sw7_b = tx0_switch_7_reg[1];
|
||||
assign tx0_sw8_v1 = tx0_switch_8_reg[0];
|
||||
assign tx0_sw8_v2 = tx0_switch_8_reg[1];
|
||||
assign tx0_sw8_v3 = tx0_switch_8_reg[2];
|
||||
assign tx0_sw9_a = tx0_switch_9_reg[0];
|
||||
assign tx0_sw9_b = tx0_switch_9_reg[1];
|
||||
assign tx0_sw10_a = tx0_switch_10_reg[0];
|
||||
assign tx0_sw10_b = tx0_switch_10_reg[1];
|
||||
assign tx0_sw11_a = tx0_switch_11_reg[0];
|
||||
assign tx0_sw11_b = tx0_switch_11_reg[1];
|
||||
assign tx0_sw13_v1 = tx0_switch_13_reg;
|
||||
assign tx0_sw14_v1 = tx0_switch_14_reg;
|
||||
|
||||
assign tx1_sw1_sw2_ctrl = tx1_switch_1_2_reg;
|
||||
assign tx1_sw3_a = tx1_switch_3_reg[0];
|
||||
assign tx1_sw3_b = tx1_switch_3_reg[1];
|
||||
assign tx1_sw4_a = tx1_switch_4_reg[0];
|
||||
assign tx1_sw4_b = tx1_switch_4_reg[1];
|
||||
assign tx1_sw5_a = tx1_switch_5_reg[0];
|
||||
assign tx1_sw5_b = tx1_switch_5_reg[1];
|
||||
assign tx1_sw6_a = tx1_switch_6_reg[0];
|
||||
assign tx1_sw6_b = tx1_switch_6_reg[1];
|
||||
assign tx1_sw7_a = tx1_switch_7_reg[0];
|
||||
assign tx1_sw7_b = tx1_switch_7_reg[1];
|
||||
assign tx1_sw8_v1 = tx1_switch_8_reg[0];
|
||||
assign tx1_sw8_v2 = tx1_switch_8_reg[1];
|
||||
assign tx1_sw8_v3 = tx1_switch_8_reg[2];
|
||||
assign tx1_sw9_a = tx1_switch_9_reg[0];
|
||||
assign tx1_sw9_b = tx1_switch_9_reg[1];
|
||||
assign tx1_sw10_a = tx1_switch_10_reg[0];
|
||||
assign tx1_sw10_b = tx1_switch_10_reg[1];
|
||||
assign tx1_sw11_a = tx1_switch_11_reg[0];
|
||||
assign tx1_sw11_b = tx1_switch_11_reg[1];
|
||||
assign tx1_sw13_v1 = tx1_switch_13_reg;
|
||||
assign tx1_sw14_v1 = tx1_switch_14_reg;
|
||||
|
||||
assign rx0_sw1_a = rx0_switch_1_reg[0];
|
||||
assign rx0_sw1_b = rx0_switch_1_reg[1];
|
||||
assign rx0_sw2_a = rx0_switch_2_reg;
|
||||
assign rx0_sw3_v1 = rx0_switch_3_reg[0];
|
||||
assign rx0_sw3_v2 = rx0_switch_3_reg[1];
|
||||
assign rx0_sw3_v3 = rx0_switch_3_reg[2];
|
||||
assign rx0_sw4_a = rx0_switch_4_reg;
|
||||
assign rx0_sw5_a = rx0_switch_5_reg[0];
|
||||
assign rx0_sw5_b = rx0_switch_5_reg[1];
|
||||
assign rx0_sw6_a = rx0_switch_6_reg[0];
|
||||
assign rx0_sw6_b = rx0_switch_6_reg[1];
|
||||
assign rx0_sw7_sw8_ctrl = rx0_switch_7_8_reg;
|
||||
assign rx0_sw9_v1 = rx0_switch_9_reg;
|
||||
assign rx0_sw10_v1 = rx0_switch_10_reg;
|
||||
assign rx0_sw11_v1 = rx0_switch_11_reg[0];
|
||||
assign rx0_sw11_v2 = rx0_switch_11_reg[1];
|
||||
assign rx0_sw11_v3 = rx0_switch_11_reg[2];
|
||||
|
||||
assign rx1_sw1_a = rx1_switch_1_reg[0];
|
||||
assign rx1_sw1_b = rx1_switch_1_reg[1];
|
||||
assign rx1_sw2_a = rx1_switch_2_reg;
|
||||
assign rx1_sw3_v1 = rx1_switch_3_reg[0];
|
||||
assign rx1_sw3_v2 = rx1_switch_3_reg[1];
|
||||
assign rx1_sw3_v3 = rx1_switch_3_reg[2];
|
||||
assign rx1_sw4_a = rx1_switch_4_reg;
|
||||
assign rx1_sw5_a = rx1_switch_5_reg[0];
|
||||
assign rx1_sw5_b = rx1_switch_5_reg[1];
|
||||
assign rx1_sw6_a = rx1_switch_6_reg[0];
|
||||
assign rx1_sw6_b = rx1_switch_6_reg[1];
|
||||
assign rx1_sw7_sw8_ctrl = rx1_switch_7_8_reg;
|
||||
assign rx1_sw9_v1 = rx1_switch_9_reg;
|
||||
assign rx1_sw10_v1 = rx1_switch_10_reg;
|
||||
assign rx1_sw11_v1 = rx1_switch_11_reg[0];
|
||||
assign rx1_sw11_v2 = rx1_switch_11_reg[1];
|
||||
assign rx1_sw11_v3 = rx1_switch_11_reg[2];
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="SWITCH_SETUP_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
||||
// <group name="SWITCH_SETUP_REGISTERS">
|
||||
// <info>
|
||||
// The following registers are used to control the path that the RF signal
|
||||
// takes for both Tx and Rx{BR/}{BR/}
|
||||
// </info>
|
||||
// <regtype name="TX_PATH_CONTROL" size="32" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// This Register controls the switches along the Tx path. Note: default
|
||||
// values refer to the RX0 path. RX1 has the same defaults, but their
|
||||
// bit values may differ.
|
||||
// </info>
|
||||
// <bitfield name="TX_SWITCH_1_2" range="0" initialvalue="0">
|
||||
// <info>
|
||||
// Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz{BR/}
|
||||
// Write 1 to select Tx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_3" range="3..2" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 3. The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See @.TX_SWITCH_4 for those controls{BR/}
|
||||
// Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/}
|
||||
// Write 3 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/}
|
||||
// Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/}
|
||||
// Write 3 to select Tx If1 Filter 1,2,3, or 50 ohm termination. See @.TX_SWITCH_4 for those controls{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_4" range="5..4" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 4. This switch path is only taken if @.TX_SWITCH_4 is set to 0.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select 50 ohm termination{BR/}
|
||||
// Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/}
|
||||
// Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/}
|
||||
// Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/}
|
||||
// Write 3 to select 50 ohm termination{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_5" range="7..6" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 5. This switch path is only taken if @.TX_SWITCH_6 is set to 0.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/}
|
||||
// Write 1 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/}
|
||||
// Write 3 to select Tx If1 Filter 50 ohm termination{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx If1 Filter 50 ohm termination{BR/}
|
||||
// Write 1 to select Tx If1 Filter 1, 3.1 GHz to 4.3 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 2, 4.3 GHz to 5.1 GHz{BR/}
|
||||
// Write 3 to select Tx If1 Filter 3, 5.1 GHz to 5.7 GHz{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_6" range="9..8" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 6.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/}
|
||||
// Write 1 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/}
|
||||
// Write 3 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See @.TX_SWITCH_5 for those controls{/font}{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx If1 Filter 1, 2, 3, or 50 ohm termination. See @.TX_SWITCH_5 for those controls{/font}{BR/}
|
||||
// Write 1 to select Tx If1 Filter 4, 5.7 GHz to 6.4 GHz{BR/}
|
||||
// Write 2 to select Tx If1 Filter 5, 6.4 GHz to 7.0 GHz{BR/}
|
||||
// Write 3 to select Tx If1 Filter 6, 7.0 GHz to 8.0 GHz{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_7" range="11..10" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 7.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select 50 ohm termination{BR/}
|
||||
// Write 1 to select no connect{BR/}
|
||||
// Write 2 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz{BR/}
|
||||
// Write 3 to select Tx lowbands RF1, RF2, RF3 path. See @.TX_SWITCH_8 for those controls{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx lowbands RF1, RF2, RF3 path. See @.TX_SWITCH_8 for those controls{BR/}
|
||||
// Write 1 to select Tx highBand RF4 path, 3.1 GHz to 8 GHz{BR/}
|
||||
// Write 2 to select no connect{BR/}
|
||||
// Write 3 to select 50 ohm termination{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_8" range="14..12" initialvalue="0">
|
||||
// <info>
|
||||
// Control for Tx Switch 8, note this is one hot encoding and not binary.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 1 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/}
|
||||
// Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/}
|
||||
// Write 4 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/}
|
||||
// Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/}
|
||||
// Write 4 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/}
|
||||
// {i}*All other values are invalid{/i}{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_9" range="17..16" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 9.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/}
|
||||
// Write 1 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/}
|
||||
// Write 2 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/}
|
||||
// Write 3 to select Tx RF4 path, 3.1 GHz to 8.0 GHz{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx RF4 path, 3.1 GHz to 8.0 GHz{BR/}
|
||||
// Write 1 to select Tx RF2 path, 1.95 GHz to 2.3 GHz{BR/}
|
||||
// Write 2 to select Tx RF1 path, 1.0 MHz to 1.95 GHz{BR/}
|
||||
// Write 3 to select Tx RF3 path, 2.3 GHz to 3.1 GHz{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_10" range="19..18" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 10.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx amplifier bypass path{BR/}
|
||||
// Write 1 to select Tx calibration loopback path{BR/}
|
||||
// Write 2 to select Tx lowband amp path. @.TX_Switch_11 must also match this path.{BR/}
|
||||
// Write 3 to select Tx highband amp path. @.TX_Switch_11 must also match this path.{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx highband amp path. @.TX_Switch_11 must also match this path.{BR/}
|
||||
// Write 1 to select Tx lowband amp path. @.TX_Switch_11 must also match this path.{BR/}
|
||||
// Write 2 to select Tx amplifier bypass path{BR/}
|
||||
// Write 3 to select Tx calibration loopback path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_11" range="21..20" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Tx Switch 11.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx Rx path, @.RX_SWITCH_1 must also select the correct path{BR/}
|
||||
// Write 1 to select Tx highband amp path. @.TX_SWITCH_10 must also match this path.{BR/}
|
||||
// Write 2 to select Tx lowband amp path. @.TX_SWITCH_10 must also match this path.{BR/}
|
||||
// Write 3 to select Tx amplifier bypass path{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx Rx path, @.RX_SWITCH_1 must also select the correct path{BR/}
|
||||
// Write 1 to select Tx amplifier bypass path{BR/}
|
||||
// Write 2 to select Tx lowband amp path. @.TX_SWITCH_10 must also match this path.{BR/}
|
||||
// Write 3 to select Tx highband amp path. @.TX_SWITCH_10 must also match this path.{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_13" range="24" initialvalue="0">
|
||||
// <info>
|
||||
// Control for Tx0 Switch 13 LO path.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx0 internal LO path{BR/}
|
||||
// Write 1 to select Tx0 external LO path{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx0 external LO path{BR/}
|
||||
// Write 1 to select Tx0 internal LO path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TX_SWITCH_14" range="26" initialvalue="0">
|
||||
// <info>
|
||||
// Control for Tx Switch 13 LO path.
|
||||
// The configuration of this switch changes between TX paths.{BR/}
|
||||
// {b}FOR TX0:{/b}{BR/}
|
||||
// Write 0 to select Tx external LO path{BR/}
|
||||
// Write 1 to select Tx internal LO path{BR/}
|
||||
// {b}FOR TX1:{/b}{BR/}
|
||||
// Write 0 to select Tx internal LO path{BR/}
|
||||
// Write 1 to select Tx external LO path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
//
|
||||
// <regtype name="RX_PATH_CONTROL" size="32" attributes="Readable|Writable">
|
||||
// <info>
|
||||
// This Register controls switches along Rx paths. Note: default
|
||||
// values refer to the RX0 path. RX1 has the same defaults, but their
|
||||
// bit values may differ.
|
||||
// </info>
|
||||
// <bitfield name="RX_SWITCH_1" range="1..0" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}
|
||||
// Control for Rx Switch 1.
|
||||
// The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 0 to select Rx calibration loopback{BR/}
|
||||
// Write 1 to select Rx 50 ohm termination path{BR/}
|
||||
// Write 2 to select Tx Rx path, @.TX_SWITCH_11 must also select the correct path{BR/}
|
||||
// Write 3 to select Rx input port{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 0 to select Rx calibration loopback{BR/}
|
||||
// Write 1 to select Tx Rx path, @.TX_SWITCH_11 must also select the correct path{BR/}
|
||||
// Write 2 to select Rx input port{BR/}
|
||||
// Write 3 to select Rx 50 ohm termination path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_2" range="2" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is the only control, and control B is pulled high{/font}{BR/}
|
||||
// Control for Rx Switch 2. The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 0 to select Rx RF3 highband path{BR/}
|
||||
// Write 1 to select Rx RF1/2 lowband path{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 0 to select Rx RF1/2 lowband path{BR/}
|
||||
// Write 1 to select Rx RF3 highband path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_3" range="6..4" initialvalue="0">
|
||||
// <info>
|
||||
// Control for Rx Switch 3, note this is one hot encoding and not binary.
|
||||
// The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 1 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/}
|
||||
// Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/}
|
||||
// Write 4 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 1 to select Rx RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/}
|
||||
// Write 2 to select Rx RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/}
|
||||
// Write 4 to select Rx RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/}
|
||||
// {i}*All other values are invalid{/i}{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_4" range="8" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is the only control, and control B is tied to ground{/font}{BR/}
|
||||
// Control for Rx Switch 4.{BR/}
|
||||
// Write 0 to select Rx RF1/2 lowband path{BR/}
|
||||
// Write 1 to select Rx RF3 highband path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_5" range="11..10" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}{BR/}
|
||||
//
|
||||
// Control for Rx Switch 5. The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_6" range="13..12" initialvalue="0">
|
||||
// <info>
|
||||
// {font color="red"}note to digital designer: control A is LSB, and control B is MSB{/font}{BR/}{BR/}
|
||||
//
|
||||
// Control for Rx Switch 6. The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 0 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 1 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 2 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 3 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 0 to select Rx RF filter 4 path, 7.0 - 8 GHz GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 1 to select Rx RF filter 3 path, 5.6 - 8 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 2 to select Rx RF filter 2 path, 4.2 - 5.6 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// Write 3 to select Rx RF filter 1 path, 3.0 - 4.2 GHz, @.RX_SWITCH_6 must also select this path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_7_8" range="14" initialvalue="0">
|
||||
// <info>
|
||||
// Shared control for Rx switch 7 and switch 8.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 0 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz{BR/}
|
||||
// Write 1 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 0 to select Rx IF2 filter 1, CF = 1060 MHz, BW = 400 MHz{BR/}
|
||||
// Write 1 to select Rx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_9" range="16" initialvalue="0">
|
||||
// <info>
|
||||
// Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 0 to select Rx internal LO path{BR/}
|
||||
// Write 1 to select Rx external LO path{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 0 to select Rx external LO path{BR/}
|
||||
// Write 1 to select Rx internal LO path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_10" range="18" initialvalue="0">
|
||||
// <info>
|
||||
// Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 0 to select Rx internal LO path{BR/}
|
||||
// Write 1 to select Rx external LO path{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 0 to select Rx external LO path{BR/}
|
||||
// Write 1 to select Rx internal LO path{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RX_SWITCH_11" range="22..20" initialvalue="0">
|
||||
// <info>
|
||||
// Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground.{BR/}{BR/}
|
||||
// The configuration of this switch changes between RX paths.{BR/}
|
||||
// {b}FOR RX0:{/b}{BR/}
|
||||
// Write 1 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/}
|
||||
// Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/}
|
||||
// Write 4 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/}
|
||||
// {b}FOR RX1:{/b}{BR/}
|
||||
// Write 1 to select Rx1 RF filter 2 path, 1.80 GHz - 2.30 GHz{BR/}
|
||||
// Write 2 to select Rx1 RF filter 1 path, 1.00 MHz - 1.80 GHz{BR/}
|
||||
// Write 4 to select Rx1 RF filter 3 path, 2.30 MHz - 3.00 GHz{BR/}
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
//
|
||||
// <register name="TX0_PATH_CONTROL" typename="TX_PATH_CONTROL" offset="0x00" count="256" step="4">
|
||||
// <info>
|
||||
// This Register controls the Tx0 paths.{br}
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="TX1_PATH_CONTROL" typename="TX_PATH_CONTROL" offset="0x400" count="256" step="4">
|
||||
// <info>
|
||||
// This Register controls the Tx1 paths.{br}
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
//
|
||||
// <register name="RX0_PATH_CONTROL" typename="RX_PATH_CONTROL" offset="0x800" count="256" step="4">
|
||||
// <info>
|
||||
// This Register controls the Rx0 paths.{br}
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
// <register name="RX1_PATH_CONTROL" typename="RX_PATH_CONTROL" offset="0xC00" count="256" step="4">
|
||||
// <info>
|
||||
// This Register controls the Rx1 paths.{br}
|
||||
// This register array can hold settings for all ATR configurations.
|
||||
// The register index equals the ATR configuration.
|
||||
// The active configuration can be selected in @.ATR_REGMAP.
|
||||
// Independently all configurations can be read/written at any time.
|
||||
// </info>
|
||||
// </register>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,30 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: spi_control_utils
|
||||
//
|
||||
// Description:
|
||||
// Contains constants and functions common to blocks that interact
|
||||
// with the wishbone spi engine.
|
||||
//
|
||||
|
||||
// SPI Master Control Register Offsets
|
||||
localparam TX_DATA_REG = 5'h00;
|
||||
localparam RX_DATA_REG = 5'h00;
|
||||
localparam CLOCK_DIVIDER_REG = 5'h14;
|
||||
localparam CONTROL_REG = 5'h10;
|
||||
localparam SS_REG = 5'h18;
|
||||
|
||||
// Simple function to return a vector of 0's with only position
|
||||
// ss_input set to 1.
|
||||
function automatic [31:0] set_ss_bit;
|
||||
input [3:0] ss_input;
|
||||
reg [31:0] ss_data;
|
||||
begin
|
||||
ss_data = 32'h0;
|
||||
ss_data[ss_input] = 1'b1;
|
||||
set_ss_bit = ss_data;
|
||||
end
|
||||
endfunction
|
||||
@@ -0,0 +1,81 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: atr_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// CURRENT_CONFIG_REG : 0x0 (atr_controller.v)
|
||||
// OPTION_REG : 0x4 (atr_controller.v)
|
||||
// SW_CONFIG_REG : 0x8 (atr_controller.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group ATR_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// Enumerated type ATR_OPTIONS
|
||||
localparam ATR_OPTIONS_SIZE = 3;
|
||||
localparam SW_DEFINED = 'h0; // ATR_OPTIONS:SW_DEFINED
|
||||
localparam CLASSIC_ATR = 'h1; // ATR_OPTIONS:CLASSIC_ATR
|
||||
localparam FPGA_STATE = 'h2; // ATR_OPTIONS:FPGA_STATE
|
||||
|
||||
// CURRENT_CONFIG_REG Register (from atr_controller.v)
|
||||
localparam CURRENT_CONFIG_REG = 'h0; // Register Offset
|
||||
localparam CURRENT_CONFIG_REG_SIZE = 32; // register width in bits
|
||||
localparam CURRENT_CONFIG_REG_MASK = 32'hFFFFFFFF;
|
||||
localparam CURRENT_RF0_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF0_CONFIG
|
||||
localparam CURRENT_RF0_CONFIG_MSB = 7; //CURRENT_CONFIG_REG:CURRENT_RF0_CONFIG
|
||||
localparam CURRENT_RF0_CONFIG = 0; //CURRENT_CONFIG_REG:CURRENT_RF0_CONFIG
|
||||
localparam CURRENT_RF1_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF1_CONFIG
|
||||
localparam CURRENT_RF1_CONFIG_MSB = 15; //CURRENT_CONFIG_REG:CURRENT_RF1_CONFIG
|
||||
localparam CURRENT_RF1_CONFIG = 8; //CURRENT_CONFIG_REG:CURRENT_RF1_CONFIG
|
||||
localparam CURRENT_RF0_DSA_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF0_DSA_CONFIG
|
||||
localparam CURRENT_RF0_DSA_CONFIG_MSB = 23; //CURRENT_CONFIG_REG:CURRENT_RF0_DSA_CONFIG
|
||||
localparam CURRENT_RF0_DSA_CONFIG = 16; //CURRENT_CONFIG_REG:CURRENT_RF0_DSA_CONFIG
|
||||
localparam CURRENT_RF1_DSA_CONFIG_SIZE = 8; //CURRENT_CONFIG_REG:CURRENT_RF1_DSA_CONFIG
|
||||
localparam CURRENT_RF1_DSA_CONFIG_MSB = 31; //CURRENT_CONFIG_REG:CURRENT_RF1_DSA_CONFIG
|
||||
localparam CURRENT_RF1_DSA_CONFIG = 24; //CURRENT_CONFIG_REG:CURRENT_RF1_DSA_CONFIG
|
||||
|
||||
// OPTION_REG Register (from atr_controller.v)
|
||||
localparam OPTION_REG = 'h4; // Register Offset
|
||||
localparam OPTION_REG_SIZE = 32; // register width in bits
|
||||
localparam OPTION_REG_MASK = 32'h3030303;
|
||||
localparam RF0_OPTION_SIZE = 2; //OPTION_REG:RF0_OPTION
|
||||
localparam RF0_OPTION_MSB = 1; //OPTION_REG:RF0_OPTION
|
||||
localparam RF0_OPTION = 0; //OPTION_REG:RF0_OPTION
|
||||
localparam RF1_OPTION_SIZE = 2; //OPTION_REG:RF1_OPTION
|
||||
localparam RF1_OPTION_MSB = 9; //OPTION_REG:RF1_OPTION
|
||||
localparam RF1_OPTION = 8; //OPTION_REG:RF1_OPTION
|
||||
localparam RF0_DSA_OPTION_SIZE = 2; //OPTION_REG:RF0_DSA_OPTION
|
||||
localparam RF0_DSA_OPTION_MSB = 17; //OPTION_REG:RF0_DSA_OPTION
|
||||
localparam RF0_DSA_OPTION = 16; //OPTION_REG:RF0_DSA_OPTION
|
||||
localparam RF1_DSA_OPTION_SIZE = 2; //OPTION_REG:RF1_DSA_OPTION
|
||||
localparam RF1_DSA_OPTION_MSB = 25; //OPTION_REG:RF1_DSA_OPTION
|
||||
localparam RF1_DSA_OPTION = 24; //OPTION_REG:RF1_DSA_OPTION
|
||||
|
||||
// SW_CONFIG_REG Register (from atr_controller.v)
|
||||
localparam SW_CONFIG_REG = 'h8; // Register Offset
|
||||
localparam SW_CONFIG_REG_SIZE = 32; // register width in bits
|
||||
localparam SW_CONFIG_REG_MASK = 32'hFFFFFFFF;
|
||||
localparam SW_RF0_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF0_CONFIG
|
||||
localparam SW_RF0_CONFIG_MSB = 7; //SW_CONFIG_REG:SW_RF0_CONFIG
|
||||
localparam SW_RF0_CONFIG = 0; //SW_CONFIG_REG:SW_RF0_CONFIG
|
||||
localparam SW_RF1_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF1_CONFIG
|
||||
localparam SW_RF1_CONFIG_MSB = 15; //SW_CONFIG_REG:SW_RF1_CONFIG
|
||||
localparam SW_RF1_CONFIG = 8; //SW_CONFIG_REG:SW_RF1_CONFIG
|
||||
localparam SW_RF0_DSA_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF0_DSA_CONFIG
|
||||
localparam SW_RF0_DSA_CONFIG_MSB = 23; //SW_CONFIG_REG:SW_RF0_DSA_CONFIG
|
||||
localparam SW_RF0_DSA_CONFIG = 16; //SW_CONFIG_REG:SW_RF0_DSA_CONFIG
|
||||
localparam SW_RF1_DSA_CONFIG_SIZE = 8; //SW_CONFIG_REG:SW_RF1_DSA_CONFIG
|
||||
localparam SW_RF1_DSA_CONFIG_MSB = 31; //SW_CONFIG_REG:SW_RF1_DSA_CONFIG
|
||||
localparam SW_RF1_DSA_CONFIG = 24; //SW_CONFIG_REG:SW_RF1_DSA_CONFIG
|
||||
@@ -0,0 +1,75 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: basic_regs_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// SLAVE_SIGNATURE : 0x0 (basic_regs.v)
|
||||
// SLAVE_REVISION : 0x4 (basic_regs.v)
|
||||
// SLAVE_OLDEST_REVISION : 0x8 (basic_regs.v)
|
||||
// SLAVE_SCRATCH : 0xC (basic_regs.v)
|
||||
// GIT_HASH_REGISTER : 0x10 (basic_regs.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group BASIC_REGS_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// Enumerated type BASIC_REGISTERS_VALUES
|
||||
localparam BASIC_REGISTERS_VALUES_SIZE = 3;
|
||||
localparam BOARD_ID_VALUE = 'h4002; // BASIC_REGISTERS_VALUES:BOARD_ID_VALUE
|
||||
localparam OLDEST_CPLD_REVISION = 'h20110611; // BASIC_REGISTERS_VALUES:OLDEST_CPLD_REVISION
|
||||
localparam CPLD_REVISION = 'h21031009; // BASIC_REGISTERS_VALUES:CPLD_REVISION
|
||||
|
||||
// SLAVE_SIGNATURE Register (from basic_regs.v)
|
||||
localparam SLAVE_SIGNATURE = 'h0; // Register Offset
|
||||
localparam SLAVE_SIGNATURE_SIZE = 32; // register width in bits
|
||||
localparam SLAVE_SIGNATURE_MASK = 32'hFFFF;
|
||||
localparam BOARD_ID_SIZE = 16; //SLAVE_SIGNATURE:BOARD_ID
|
||||
localparam BOARD_ID_MSB = 15; //SLAVE_SIGNATURE:BOARD_ID
|
||||
localparam BOARD_ID = 0; //SLAVE_SIGNATURE:BOARD_ID
|
||||
|
||||
// SLAVE_REVISION Register (from basic_regs.v)
|
||||
localparam SLAVE_REVISION = 'h4; // Register Offset
|
||||
localparam SLAVE_REVISION_SIZE = 32; // register width in bits
|
||||
localparam SLAVE_REVISION_MASK = 32'hFFFFFFFF;
|
||||
localparam REVISION_REG_SIZE = 32; //SLAVE_REVISION:REVISION_REG
|
||||
localparam REVISION_REG_MSB = 31; //SLAVE_REVISION:REVISION_REG
|
||||
localparam REVISION_REG = 0; //SLAVE_REVISION:REVISION_REG
|
||||
|
||||
// SLAVE_OLDEST_REVISION Register (from basic_regs.v)
|
||||
localparam SLAVE_OLDEST_REVISION = 'h8; // Register Offset
|
||||
localparam SLAVE_OLDEST_REVISION_SIZE = 32; // register width in bits
|
||||
localparam SLAVE_OLDEST_REVISION_MASK = 32'hFFFFFFFF;
|
||||
localparam OLDEST_REVISION_REG_SIZE = 32; //SLAVE_OLDEST_REVISION:OLDEST_REVISION_REG
|
||||
localparam OLDEST_REVISION_REG_MSB = 31; //SLAVE_OLDEST_REVISION:OLDEST_REVISION_REG
|
||||
localparam OLDEST_REVISION_REG = 0; //SLAVE_OLDEST_REVISION:OLDEST_REVISION_REG
|
||||
|
||||
// SLAVE_SCRATCH Register (from basic_regs.v)
|
||||
localparam SLAVE_SCRATCH = 'hC; // Register Offset
|
||||
localparam SLAVE_SCRATCH_SIZE = 32; // register width in bits
|
||||
localparam SLAVE_SCRATCH_MASK = 32'hFFFFFFFF;
|
||||
localparam SCRATCH_REG_SIZE = 32; //SLAVE_SCRATCH:SCRATCH_REG
|
||||
localparam SCRATCH_REG_MSB = 31; //SLAVE_SCRATCH:SCRATCH_REG
|
||||
localparam SCRATCH_REG = 0; //SLAVE_SCRATCH:SCRATCH_REG
|
||||
|
||||
// GIT_HASH_REGISTER Register (from basic_regs.v)
|
||||
localparam GIT_HASH_REGISTER = 'h10; // Register Offset
|
||||
localparam GIT_HASH_REGISTER_SIZE = 32; // register width in bits
|
||||
localparam GIT_HASH_REGISTER_MASK = 32'hFFFFFFFF;
|
||||
localparam GIT_HASH_SIZE = 28; //GIT_HASH_REGISTER:GIT_HASH
|
||||
localparam GIT_HASH_MSB = 27; //GIT_HASH_REGISTER:GIT_HASH
|
||||
localparam GIT_HASH = 0; //GIT_HASH_REGISTER:GIT_HASH
|
||||
localparam GIT_CLEAN_SIZE = 4; //GIT_HASH_REGISTER:GIT_CLEAN
|
||||
localparam GIT_CLEAN_MSB = 31; //GIT_HASH_REGISTER:GIT_CLEAN
|
||||
localparam GIT_CLEAN = 28; //GIT_HASH_REGISTER:GIT_CLEAN
|
||||
@@ -0,0 +1,58 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: db_control_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// ATR_CONTROLLER_REGS : 0x0 (zbx_top_cpld.v)
|
||||
// LO_CONTROL_REGS : 0x20 (zbx_top_cpld.v)
|
||||
// LED_SETUP_REGS : 0x400 (zbx_top_cpld.v)
|
||||
// SWITCH_SETUP_REGS : 0x1000 (zbx_top_cpld.v)
|
||||
// DSA_SETUP_REGS : 0x2000 (zbx_top_cpld.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group DB_CONTROL_WINDOWS
|
||||
//===============================================================================
|
||||
|
||||
// ATR_CONTROLLER_REGS Window (from zbx_top_cpld.v)
|
||||
localparam ATR_CONTROLLER_REGS = 'h0; // Window Offset
|
||||
localparam ATR_CONTROLLER_REGS_SIZE = 'h20; // size in bytes
|
||||
|
||||
// LO_CONTROL_REGS Window (from zbx_top_cpld.v)
|
||||
localparam LO_CONTROL_REGS = 'h20; // Window Offset
|
||||
localparam LO_CONTROL_REGS_SIZE = 'h3E0; // size in bytes
|
||||
|
||||
// LED_SETUP_REGS Window (from zbx_top_cpld.v)
|
||||
localparam LED_SETUP_REGS = 'h400; // Window Offset
|
||||
localparam LED_SETUP_REGS_SIZE = 'hC00; // size in bytes
|
||||
|
||||
// SWITCH_SETUP_REGS Window (from zbx_top_cpld.v)
|
||||
localparam SWITCH_SETUP_REGS = 'h1000; // Window Offset
|
||||
localparam SWITCH_SETUP_REGS_SIZE = 'h1000; // size in bytes
|
||||
|
||||
// DSA_SETUP_REGS Window (from zbx_top_cpld.v)
|
||||
localparam DSA_SETUP_REGS = 'h2000; // Window Offset
|
||||
localparam DSA_SETUP_REGS_SIZE = 'h3000; // size in bytes
|
||||
|
||||
//===============================================================================
|
||||
// Register Group REGISTER_ENDPOINTS
|
||||
//===============================================================================
|
||||
|
||||
// Enumerated type REGISTER_BLOCKS
|
||||
localparam REGISTER_BLOCKS_SIZE = 5;
|
||||
localparam ATR_REGISTERS = 'h0; // REGISTER_BLOCKS:ATR_REGISTERS
|
||||
localparam LED_REGISTERS = 'h1; // REGISTER_BLOCKS:LED_REGISTERS
|
||||
localparam LO_SPI = 'h2; // REGISTER_BLOCKS:LO_SPI
|
||||
localparam SW_CONTROL = 'h3; // REGISTER_BLOCKS:SW_CONTROL
|
||||
localparam DSA_CONTROL = 'h4; // REGISTER_BLOCKS:DSA_CONTROL
|
||||
@@ -0,0 +1,162 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: dsa_setup_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// TX0_DSA_ATR : 0x0 (dsa_control.v)
|
||||
// TX1_DSA_ATR : 0x400 (dsa_control.v)
|
||||
// RX0_DSA_ATR : 0x800 (dsa_control.v)
|
||||
// RX1_DSA_ATR : 0xC00 (dsa_control.v)
|
||||
// TX0_DSA_TABLE_SELECT : 0x1000 (dsa_control.v)
|
||||
// TX1_DSA_TABLE_SELECT : 0x1400 (dsa_control.v)
|
||||
// RX0_DSA_TABLE_SELECT : 0x1800 (dsa_control.v)
|
||||
// RX1_DSA_TABLE_SELECT : 0x1C00 (dsa_control.v)
|
||||
// TX0_DSA_TABLE : 0x2000 (dsa_control.v)
|
||||
// TX1_DSA_TABLE : 0x2400 (dsa_control.v)
|
||||
// RX0_DSA_TABLE : 0x2800 (dsa_control.v)
|
||||
// RX1_DSA_TABLE : 0x2C00 (dsa_control.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
// DSA_TABLE_CONTROL Type (from dsa_control.v)
|
||||
localparam DSA_TABLE_CONTROL_SIZE = 32;
|
||||
localparam DSA_TABLE_CONTROL_MASK = 32'hFF;
|
||||
localparam TABLE_INDEX_SIZE = 8; //DSA_TABLE_CONTROL:TABLE_INDEX
|
||||
localparam TABLE_INDEX_MSB = 7; //DSA_TABLE_CONTROL:TABLE_INDEX
|
||||
localparam TABLE_INDEX = 0; //DSA_TABLE_CONTROL:TABLE_INDEX
|
||||
|
||||
// RX_DSA_CONTROL Type (from dsa_control.v)
|
||||
localparam RX_DSA_CONTROL_SIZE = 32;
|
||||
localparam RX_DSA_CONTROL_MASK = 32'hFFFF;
|
||||
localparam RX_DSA1_SIZE = 4; //RX_DSA_CONTROL:RX_DSA1
|
||||
localparam RX_DSA1_MSB = 3; //RX_DSA_CONTROL:RX_DSA1
|
||||
localparam RX_DSA1 = 0; //RX_DSA_CONTROL:RX_DSA1
|
||||
localparam RX_DSA2_SIZE = 4; //RX_DSA_CONTROL:RX_DSA2
|
||||
localparam RX_DSA2_MSB = 7; //RX_DSA_CONTROL:RX_DSA2
|
||||
localparam RX_DSA2 = 4; //RX_DSA_CONTROL:RX_DSA2
|
||||
localparam RX_DSA3_A_SIZE = 4; //RX_DSA_CONTROL:RX_DSA3_A
|
||||
localparam RX_DSA3_A_MSB = 11; //RX_DSA_CONTROL:RX_DSA3_A
|
||||
localparam RX_DSA3_A = 8; //RX_DSA_CONTROL:RX_DSA3_A
|
||||
localparam RX_DSA3_B_SIZE = 4; //RX_DSA_CONTROL:RX_DSA3_B
|
||||
localparam RX_DSA3_B_MSB = 15; //RX_DSA_CONTROL:RX_DSA3_B
|
||||
localparam RX_DSA3_B = 12; //RX_DSA_CONTROL:RX_DSA3_B
|
||||
|
||||
// TX_DSA_CONTROL Type (from dsa_control.v)
|
||||
localparam TX_DSA_CONTROL_SIZE = 32;
|
||||
localparam TX_DSA_CONTROL_MASK = 32'h1F1F;
|
||||
localparam TX_DSA1_SIZE = 5; //TX_DSA_CONTROL:TX_DSA1
|
||||
localparam TX_DSA1_MSB = 4; //TX_DSA_CONTROL:TX_DSA1
|
||||
localparam TX_DSA1 = 0; //TX_DSA_CONTROL:TX_DSA1
|
||||
localparam TX_DSA2_SIZE = 5; //TX_DSA_CONTROL:TX_DSA2
|
||||
localparam TX_DSA2_MSB = 12; //TX_DSA_CONTROL:TX_DSA2
|
||||
localparam TX_DSA2 = 8; //TX_DSA_CONTROL:TX_DSA2
|
||||
|
||||
//===============================================================================
|
||||
// Register Group DSA_SETUP_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// TX0_DSA_ATR Register (from dsa_control.v)
|
||||
localparam TX0_DSA_ATR_COUNT = 256; // Number of elements in array
|
||||
|
||||
// TX1_DSA_ATR Register (from dsa_control.v)
|
||||
localparam TX1_DSA_ATR_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX0_DSA_ATR Register (from dsa_control.v)
|
||||
localparam RX0_DSA_ATR_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX1_DSA_ATR Register (from dsa_control.v)
|
||||
localparam RX1_DSA_ATR_COUNT = 256; // Number of elements in array
|
||||
|
||||
// TX0_DSA_TABLE_SELECT Register (from dsa_control.v)
|
||||
localparam TX0_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array
|
||||
|
||||
// TX1_DSA_TABLE_SELECT Register (from dsa_control.v)
|
||||
localparam TX1_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX0_DSA_TABLE_SELECT Register (from dsa_control.v)
|
||||
localparam RX0_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX1_DSA_TABLE_SELECT Register (from dsa_control.v)
|
||||
localparam RX1_DSA_TABLE_SELECT_COUNT = 256; // Number of elements in array
|
||||
|
||||
// TX0_DSA_TABLE Register (from dsa_control.v)
|
||||
localparam TX0_DSA_TABLE_COUNT = 256; // Number of elements in array
|
||||
|
||||
// TX1_DSA_TABLE Register (from dsa_control.v)
|
||||
localparam TX1_DSA_TABLE_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX0_DSA_TABLE Register (from dsa_control.v)
|
||||
localparam RX0_DSA_TABLE_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX1_DSA_TABLE Register (from dsa_control.v)
|
||||
localparam RX1_DSA_TABLE_COUNT = 256; // Number of elements in array
|
||||
|
||||
// Return the offset of an element of register array TX0_DSA_ATR
|
||||
function integer TX0_DSA_ATR (input integer i);
|
||||
TX0_DSA_ATR = (i * 'h4) + 'h0;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array TX1_DSA_ATR
|
||||
function integer TX1_DSA_ATR (input integer i);
|
||||
TX1_DSA_ATR = (i * 'h4) + 'h400;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX0_DSA_ATR
|
||||
function integer RX0_DSA_ATR (input integer i);
|
||||
RX0_DSA_ATR = (i * 'h4) + 'h800;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX1_DSA_ATR
|
||||
function integer RX1_DSA_ATR (input integer i);
|
||||
RX1_DSA_ATR = (i * 'h4) + 'hC00;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array TX0_DSA_TABLE_SELECT
|
||||
function integer TX0_DSA_TABLE_SELECT (input integer i);
|
||||
TX0_DSA_TABLE_SELECT = (i * 'h4) + 'h1000;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array TX1_DSA_TABLE_SELECT
|
||||
function integer TX1_DSA_TABLE_SELECT (input integer i);
|
||||
TX1_DSA_TABLE_SELECT = (i * 'h4) + 'h1400;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX0_DSA_TABLE_SELECT
|
||||
function integer RX0_DSA_TABLE_SELECT (input integer i);
|
||||
RX0_DSA_TABLE_SELECT = (i * 'h4) + 'h1800;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX1_DSA_TABLE_SELECT
|
||||
function integer RX1_DSA_TABLE_SELECT (input integer i);
|
||||
RX1_DSA_TABLE_SELECT = (i * 'h4) + 'h1C00;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array TX0_DSA_TABLE
|
||||
function integer TX0_DSA_TABLE (input integer i);
|
||||
TX0_DSA_TABLE = (i * 'h4) + 'h2000;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array TX1_DSA_TABLE
|
||||
function integer TX1_DSA_TABLE (input integer i);
|
||||
TX1_DSA_TABLE = (i * 'h4) + 'h2400;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX0_DSA_TABLE
|
||||
function integer RX0_DSA_TABLE (input integer i);
|
||||
RX0_DSA_TABLE = (i * 'h4) + 'h2800;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX1_DSA_TABLE
|
||||
function integer RX1_DSA_TABLE (input integer i);
|
||||
RX1_DSA_TABLE = (i * 'h4) + 'h2C00;
|
||||
endfunction
|
||||
@@ -0,0 +1,31 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: gpio_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// BASE_WINDOW_GPIO : 0x0 (zbx_top_cpld.v)
|
||||
// DB_CONTROL_WINDOW_GPIO : 0x1000 (zbx_top_cpld.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group GPIO_REGMAP_WINDOWS
|
||||
//===============================================================================
|
||||
|
||||
// BASE_WINDOW_GPIO Window (from zbx_top_cpld.v)
|
||||
localparam BASE_WINDOW_GPIO = 'h0; // Window Offset
|
||||
localparam BASE_WINDOW_GPIO_SIZE = 'h20; // size in bytes
|
||||
|
||||
// DB_CONTROL_WINDOW_GPIO Window (from zbx_top_cpld.v)
|
||||
localparam DB_CONTROL_WINDOW_GPIO = 'h1000; // Window Offset
|
||||
localparam DB_CONTROL_WINDOW_GPIO_SIZE = 'h5000; // size in bytes
|
||||
@@ -0,0 +1,46 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: led_setup_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// LED_CONTROL : 0x0 (led_control.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
// LED_CONTROL_TYPE Type (from led_control.v)
|
||||
localparam LED_CONTROL_TYPE_SIZE = 32;
|
||||
localparam LED_CONTROL_TYPE_MASK = 32'h70007;
|
||||
localparam CH0_RX2_LED_EN_SIZE = 1; //LED_CONTROL_TYPE:CH0_RX2_LED_EN
|
||||
localparam CH0_RX2_LED_EN_MSB = 0; //LED_CONTROL_TYPE:CH0_RX2_LED_EN
|
||||
localparam CH0_RX2_LED_EN = 0; //LED_CONTROL_TYPE:CH0_RX2_LED_EN
|
||||
localparam CH0_TRX1_LED_EN_SIZE = 2; //LED_CONTROL_TYPE:CH0_TRX1_LED_EN
|
||||
localparam CH0_TRX1_LED_EN_MSB = 2; //LED_CONTROL_TYPE:CH0_TRX1_LED_EN
|
||||
localparam CH0_TRX1_LED_EN = 1; //LED_CONTROL_TYPE:CH0_TRX1_LED_EN
|
||||
localparam CH1_RX2_LED_EN_SIZE = 1; //LED_CONTROL_TYPE:CH1_RX2_LED_EN
|
||||
localparam CH1_RX2_LED_EN_MSB = 16; //LED_CONTROL_TYPE:CH1_RX2_LED_EN
|
||||
localparam CH1_RX2_LED_EN = 16; //LED_CONTROL_TYPE:CH1_RX2_LED_EN
|
||||
localparam CH1_TRX1_LED_EN_SIZE = 2; //LED_CONTROL_TYPE:CH1_TRX1_LED_EN
|
||||
localparam CH1_TRX1_LED_EN_MSB = 18; //LED_CONTROL_TYPE:CH1_TRX1_LED_EN
|
||||
localparam CH1_TRX1_LED_EN = 17; //LED_CONTROL_TYPE:CH1_TRX1_LED_EN
|
||||
|
||||
//===============================================================================
|
||||
// Register Group LED_SETUP_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// LED_CONTROL Register (from led_control.v)
|
||||
localparam LED_CONTROL_COUNT = 256; // Number of elements in array
|
||||
|
||||
// Return the offset of an element of register array LED_CONTROL
|
||||
function integer LED_CONTROL (input integer i);
|
||||
LED_CONTROL = (i * 'h4) + 'h0;
|
||||
endfunction
|
||||
@@ -0,0 +1,110 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: lo_control_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// LO_SPI_SETUP/LO_SPI_STATUS : 0x0 (lo_control.v, lo_control.v)
|
||||
// LO_PULSE_SYNC : 0x4 (lo_control.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group LO_SPI_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// Enumerated type LO_CHIP_SELECT
|
||||
localparam LO_CHIP_SELECT_SIZE = 8;
|
||||
localparam TX0_LO1 = 'h0; // LO_CHIP_SELECT:TX0_LO1
|
||||
localparam TX0_LO2 = 'h1; // LO_CHIP_SELECT:TX0_LO2
|
||||
localparam TX1_LO1 = 'h2; // LO_CHIP_SELECT:TX1_LO1
|
||||
localparam TX1_LO2 = 'h3; // LO_CHIP_SELECT:TX1_LO2
|
||||
localparam RX0_LO1 = 'h4; // LO_CHIP_SELECT:RX0_LO1
|
||||
localparam RX0_LO2 = 'h5; // LO_CHIP_SELECT:RX0_LO2
|
||||
localparam RX1_LO1 = 'h6; // LO_CHIP_SELECT:RX1_LO1
|
||||
localparam RX1_LO2 = 'h7; // LO_CHIP_SELECT:RX1_LO2
|
||||
|
||||
// LO_SPI_SETUP Register (from lo_control.v)
|
||||
localparam LO_SPI_SETUP = 'h0; // Register Offset
|
||||
localparam LO_SPI_SETUP_SIZE = 32; // register width in bits
|
||||
localparam LO_SPI_SETUP_MASK = 32'h17FFFFFF;
|
||||
localparam LO_SPI_WT_DATA_SIZE = 16; //LO_SPI_SETUP:LO_SPI_WT_DATA
|
||||
localparam LO_SPI_WT_DATA_MSB = 15; //LO_SPI_SETUP:LO_SPI_WT_DATA
|
||||
localparam LO_SPI_WT_DATA = 0; //LO_SPI_SETUP:LO_SPI_WT_DATA
|
||||
localparam LO_SPI_WT_ADDR_SIZE = 7; //LO_SPI_SETUP:LO_SPI_WT_ADDR
|
||||
localparam LO_SPI_WT_ADDR_MSB = 22; //LO_SPI_SETUP:LO_SPI_WT_ADDR
|
||||
localparam LO_SPI_WT_ADDR = 16; //LO_SPI_SETUP:LO_SPI_WT_ADDR
|
||||
localparam LO_SPI_RD_SIZE = 1; //LO_SPI_SETUP:LO_SPI_RD
|
||||
localparam LO_SPI_RD_MSB = 23; //LO_SPI_SETUP:LO_SPI_RD
|
||||
localparam LO_SPI_RD = 23; //LO_SPI_SETUP:LO_SPI_RD
|
||||
localparam LO_SELECT_SIZE = 3; //LO_SPI_SETUP:LO_SELECT
|
||||
localparam LO_SELECT_MSB = 26; //LO_SPI_SETUP:LO_SELECT
|
||||
localparam LO_SELECT = 24; //LO_SPI_SETUP:LO_SELECT
|
||||
localparam LO_SPI_START_TRANSACTION_SIZE = 1; //LO_SPI_SETUP:LO_SPI_START_TRANSACTION
|
||||
localparam LO_SPI_START_TRANSACTION_MSB = 28; //LO_SPI_SETUP:LO_SPI_START_TRANSACTION
|
||||
localparam LO_SPI_START_TRANSACTION = 28; //LO_SPI_SETUP:LO_SPI_START_TRANSACTION
|
||||
|
||||
// LO_SPI_STATUS Register (from lo_control.v)
|
||||
localparam LO_SPI_STATUS = 'h0; // Register Offset
|
||||
localparam LO_SPI_STATUS_SIZE = 32; // register width in bits
|
||||
localparam LO_SPI_STATUS_MASK = 32'hC77FFFFF;
|
||||
localparam LO_SPI_RD_DATA_SIZE = 16; //LO_SPI_STATUS:LO_SPI_RD_DATA
|
||||
localparam LO_SPI_RD_DATA_MSB = 15; //LO_SPI_STATUS:LO_SPI_RD_DATA
|
||||
localparam LO_SPI_RD_DATA = 0; //LO_SPI_STATUS:LO_SPI_RD_DATA
|
||||
localparam LO_SPI_RD_ADDR_SIZE = 7; //LO_SPI_STATUS:LO_SPI_RD_ADDR
|
||||
localparam LO_SPI_RD_ADDR_MSB = 22; //LO_SPI_STATUS:LO_SPI_RD_ADDR
|
||||
localparam LO_SPI_RD_ADDR = 16; //LO_SPI_STATUS:LO_SPI_RD_ADDR
|
||||
localparam LO_SELECT_STATUS_SIZE = 3; //LO_SPI_STATUS:LO_SELECT_STATUS
|
||||
localparam LO_SELECT_STATUS_MSB = 26; //LO_SPI_STATUS:LO_SELECT_STATUS
|
||||
localparam LO_SELECT_STATUS = 24; //LO_SPI_STATUS:LO_SELECT_STATUS
|
||||
localparam LO_SPI_READY_SIZE = 1; //LO_SPI_STATUS:LO_SPI_READY
|
||||
localparam LO_SPI_READY_MSB = 30; //LO_SPI_STATUS:LO_SPI_READY
|
||||
localparam LO_SPI_READY = 30; //LO_SPI_STATUS:LO_SPI_READY
|
||||
localparam LO_SPI_DATA_VALID_SIZE = 1; //LO_SPI_STATUS:LO_SPI_DATA_VALID
|
||||
localparam LO_SPI_DATA_VALID_MSB = 31; //LO_SPI_STATUS:LO_SPI_DATA_VALID
|
||||
localparam LO_SPI_DATA_VALID = 31; //LO_SPI_STATUS:LO_SPI_DATA_VALID
|
||||
|
||||
//===============================================================================
|
||||
// Register Group LO_SYNC_REGS
|
||||
//===============================================================================
|
||||
|
||||
// LO_PULSE_SYNC Register (from lo_control.v)
|
||||
localparam LO_PULSE_SYNC = 'h4; // Register Offset
|
||||
localparam LO_PULSE_SYNC_SIZE = 32; // register width in bits
|
||||
localparam LO_PULSE_SYNC_MASK = 32'h1FF;
|
||||
localparam PULSE_TX0_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX0_LO1_SYNC
|
||||
localparam PULSE_TX0_LO1_SYNC_MSB = 0; //LO_PULSE_SYNC:PULSE_TX0_LO1_SYNC
|
||||
localparam PULSE_TX0_LO1_SYNC = 0; //LO_PULSE_SYNC:PULSE_TX0_LO1_SYNC
|
||||
localparam PULSE_TX0_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX0_LO2_SYNC
|
||||
localparam PULSE_TX0_LO2_SYNC_MSB = 1; //LO_PULSE_SYNC:PULSE_TX0_LO2_SYNC
|
||||
localparam PULSE_TX0_LO2_SYNC = 1; //LO_PULSE_SYNC:PULSE_TX0_LO2_SYNC
|
||||
localparam PULSE_TX1_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX1_LO1_SYNC
|
||||
localparam PULSE_TX1_LO1_SYNC_MSB = 2; //LO_PULSE_SYNC:PULSE_TX1_LO1_SYNC
|
||||
localparam PULSE_TX1_LO1_SYNC = 2; //LO_PULSE_SYNC:PULSE_TX1_LO1_SYNC
|
||||
localparam PULSE_TX1_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_TX1_LO2_SYNC
|
||||
localparam PULSE_TX1_LO2_SYNC_MSB = 3; //LO_PULSE_SYNC:PULSE_TX1_LO2_SYNC
|
||||
localparam PULSE_TX1_LO2_SYNC = 3; //LO_PULSE_SYNC:PULSE_TX1_LO2_SYNC
|
||||
localparam PULSE_RX0_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX0_LO1_SYNC
|
||||
localparam PULSE_RX0_LO1_SYNC_MSB = 4; //LO_PULSE_SYNC:PULSE_RX0_LO1_SYNC
|
||||
localparam PULSE_RX0_LO1_SYNC = 4; //LO_PULSE_SYNC:PULSE_RX0_LO1_SYNC
|
||||
localparam PULSE_RX0_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX0_LO2_SYNC
|
||||
localparam PULSE_RX0_LO2_SYNC_MSB = 5; //LO_PULSE_SYNC:PULSE_RX0_LO2_SYNC
|
||||
localparam PULSE_RX0_LO2_SYNC = 5; //LO_PULSE_SYNC:PULSE_RX0_LO2_SYNC
|
||||
localparam PULSE_RX1_LO1_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX1_LO1_SYNC
|
||||
localparam PULSE_RX1_LO1_SYNC_MSB = 6; //LO_PULSE_SYNC:PULSE_RX1_LO1_SYNC
|
||||
localparam PULSE_RX1_LO1_SYNC = 6; //LO_PULSE_SYNC:PULSE_RX1_LO1_SYNC
|
||||
localparam PULSE_RX1_LO2_SYNC_SIZE = 1; //LO_PULSE_SYNC:PULSE_RX1_LO2_SYNC
|
||||
localparam PULSE_RX1_LO2_SYNC_MSB = 7; //LO_PULSE_SYNC:PULSE_RX1_LO2_SYNC
|
||||
localparam PULSE_RX1_LO2_SYNC = 7; //LO_PULSE_SYNC:PULSE_RX1_LO2_SYNC
|
||||
localparam BYPASS_SYNC_REGISTER_SIZE = 1; //LO_PULSE_SYNC:BYPASS_SYNC_REGISTER
|
||||
localparam BYPASS_SYNC_REGISTER_MSB = 8; //LO_PULSE_SYNC:BYPASS_SYNC_REGISTER
|
||||
localparam BYPASS_SYNC_REGISTER = 8; //LO_PULSE_SYNC:BYPASS_SYNC_REGISTER
|
||||
@@ -0,0 +1,57 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: power_regs_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// RF_POWER_CONTROL : 0x0 (power_regs.v)
|
||||
// RF_POWER_STATUS : 0x4 (power_regs.v)
|
||||
// PRC_CONTROL : 0x8 (power_regs.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group POWER_REGS_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// RF_POWER_CONTROL Register (from power_regs.v)
|
||||
localparam RF_POWER_CONTROL = 'h0; // Register Offset
|
||||
localparam RF_POWER_CONTROL_SIZE = 32; // register width in bits
|
||||
localparam RF_POWER_CONTROL_MASK = 32'h7;
|
||||
localparam ENABLE_TX_7V0_SIZE = 1; //RF_POWER_CONTROL:ENABLE_TX_7V0
|
||||
localparam ENABLE_TX_7V0_MSB = 0; //RF_POWER_CONTROL:ENABLE_TX_7V0
|
||||
localparam ENABLE_TX_7V0 = 0; //RF_POWER_CONTROL:ENABLE_TX_7V0
|
||||
localparam ENABLE_RX_7V0_SIZE = 1; //RF_POWER_CONTROL:ENABLE_RX_7V0
|
||||
localparam ENABLE_RX_7V0_MSB = 1; //RF_POWER_CONTROL:ENABLE_RX_7V0
|
||||
localparam ENABLE_RX_7V0 = 1; //RF_POWER_CONTROL:ENABLE_RX_7V0
|
||||
localparam ENABLE_3V3_SIZE = 1; //RF_POWER_CONTROL:ENABLE_3v3
|
||||
localparam ENABLE_3V3_MSB = 2; //RF_POWER_CONTROL:ENABLE_3v3
|
||||
localparam ENABLE_3V3 = 2; //RF_POWER_CONTROL:ENABLE_3v3
|
||||
|
||||
// RF_POWER_STATUS Register (from power_regs.v)
|
||||
localparam RF_POWER_STATUS = 'h4; // Register Offset
|
||||
localparam RF_POWER_STATUS_SIZE = 32; // register width in bits
|
||||
localparam RF_POWER_STATUS_MASK = 32'h3;
|
||||
localparam P7V_A_STATUS_SIZE = 1; //RF_POWER_STATUS:P7V_A_STATUS
|
||||
localparam P7V_A_STATUS_MSB = 0; //RF_POWER_STATUS:P7V_A_STATUS
|
||||
localparam P7V_A_STATUS = 0; //RF_POWER_STATUS:P7V_A_STATUS
|
||||
localparam P7V_B_STATUS_SIZE = 1; //RF_POWER_STATUS:P7V_B_STATUS
|
||||
localparam P7V_B_STATUS_MSB = 1; //RF_POWER_STATUS:P7V_B_STATUS
|
||||
localparam P7V_B_STATUS = 1; //RF_POWER_STATUS:P7V_B_STATUS
|
||||
|
||||
// PRC_CONTROL Register (from power_regs.v)
|
||||
localparam PRC_CONTROL = 'h8; // Register Offset
|
||||
localparam PRC_CONTROL_SIZE = 32; // register width in bits
|
||||
localparam PRC_CONTROL_MASK = 32'h1;
|
||||
localparam PLL_REF_CLOCK_ENABLE_SIZE = 1; //PRC_CONTROL:PLL_REF_CLOCK_ENABLE
|
||||
localparam PLL_REF_CLOCK_ENABLE_MSB = 0; //PRC_CONTROL:PLL_REF_CLOCK_ENABLE
|
||||
localparam PLL_REF_CLOCK_ENABLE = 0; //PRC_CONTROL:PLL_REF_CLOCK_ENABLE
|
||||
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: spi_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// BASE_WINDOW_SPI : 0x0 (zbx_top_cpld.v)
|
||||
// RECONFIG : 0x20 (zbx_top_cpld.v)
|
||||
// POWER_REGS : 0x40 (zbx_top_cpld.v)
|
||||
// DB_CONTROL_WINDOW_SPI : 0x1000 (zbx_top_cpld.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
//===============================================================================
|
||||
// Register Group SPI_REGMAP_WINDOWS
|
||||
//===============================================================================
|
||||
|
||||
// BASE_WINDOW_SPI Window (from zbx_top_cpld.v)
|
||||
localparam BASE_WINDOW_SPI = 'h0; // Window Offset
|
||||
localparam BASE_WINDOW_SPI_SIZE = 'h20; // size in bytes
|
||||
|
||||
// RECONFIG Window (from zbx_top_cpld.v)
|
||||
localparam RECONFIG = 'h20; // Window Offset
|
||||
localparam RECONFIG_SIZE = 'h20; // size in bytes
|
||||
|
||||
// POWER_REGS Window (from zbx_top_cpld.v)
|
||||
localparam POWER_REGS = 'h40; // Window Offset
|
||||
localparam POWER_REGS_SIZE = 'h20; // size in bytes
|
||||
|
||||
// DB_CONTROL_WINDOW_SPI Window (from zbx_top_cpld.v)
|
||||
localparam DB_CONTROL_WINDOW_SPI = 'h1000; // Window Offset
|
||||
localparam DB_CONTROL_WINDOW_SPI_SIZE = 'h5000; // size in bytes
|
||||
@@ -0,0 +1,131 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, A National Instruments Company
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: switch_setup_regmap_utils.vh
|
||||
// Description:
|
||||
// The constants in this file are autogenerated by XmlParse.
|
||||
|
||||
//===============================================================================
|
||||
// A numerically ordered list of registers and their HDL source files
|
||||
//===============================================================================
|
||||
|
||||
// TX0_PATH_CONTROL : 0x0 (switch_control.v)
|
||||
// TX1_PATH_CONTROL : 0x400 (switch_control.v)
|
||||
// RX0_PATH_CONTROL : 0x800 (switch_control.v)
|
||||
// RX1_PATH_CONTROL : 0xC00 (switch_control.v)
|
||||
|
||||
//===============================================================================
|
||||
// RegTypes
|
||||
//===============================================================================
|
||||
|
||||
// RX_PATH_CONTROL Type (from switch_control.v)
|
||||
localparam RX_PATH_CONTROL_SIZE = 32;
|
||||
localparam RX_PATH_CONTROL_MASK = 32'h757D77;
|
||||
localparam RX_SWITCH_1_SIZE = 2; //RX_PATH_CONTROL:RX_SWITCH_1
|
||||
localparam RX_SWITCH_1_MSB = 1; //RX_PATH_CONTROL:RX_SWITCH_1
|
||||
localparam RX_SWITCH_1 = 0; //RX_PATH_CONTROL:RX_SWITCH_1
|
||||
localparam RX_SWITCH_2_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_2
|
||||
localparam RX_SWITCH_2_MSB = 2; //RX_PATH_CONTROL:RX_SWITCH_2
|
||||
localparam RX_SWITCH_2 = 2; //RX_PATH_CONTROL:RX_SWITCH_2
|
||||
localparam RX_SWITCH_3_SIZE = 3; //RX_PATH_CONTROL:RX_SWITCH_3
|
||||
localparam RX_SWITCH_3_MSB = 6; //RX_PATH_CONTROL:RX_SWITCH_3
|
||||
localparam RX_SWITCH_3 = 4; //RX_PATH_CONTROL:RX_SWITCH_3
|
||||
localparam RX_SWITCH_4_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_4
|
||||
localparam RX_SWITCH_4_MSB = 8; //RX_PATH_CONTROL:RX_SWITCH_4
|
||||
localparam RX_SWITCH_4 = 8; //RX_PATH_CONTROL:RX_SWITCH_4
|
||||
localparam RX_SWITCH_5_SIZE = 2; //RX_PATH_CONTROL:RX_SWITCH_5
|
||||
localparam RX_SWITCH_5_MSB = 11; //RX_PATH_CONTROL:RX_SWITCH_5
|
||||
localparam RX_SWITCH_5 = 10; //RX_PATH_CONTROL:RX_SWITCH_5
|
||||
localparam RX_SWITCH_6_SIZE = 2; //RX_PATH_CONTROL:RX_SWITCH_6
|
||||
localparam RX_SWITCH_6_MSB = 13; //RX_PATH_CONTROL:RX_SWITCH_6
|
||||
localparam RX_SWITCH_6 = 12; //RX_PATH_CONTROL:RX_SWITCH_6
|
||||
localparam RX_SWITCH_7_8_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_7_8
|
||||
localparam RX_SWITCH_7_8_MSB = 14; //RX_PATH_CONTROL:RX_SWITCH_7_8
|
||||
localparam RX_SWITCH_7_8 = 14; //RX_PATH_CONTROL:RX_SWITCH_7_8
|
||||
localparam RX_SWITCH_9_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_9
|
||||
localparam RX_SWITCH_9_MSB = 16; //RX_PATH_CONTROL:RX_SWITCH_9
|
||||
localparam RX_SWITCH_9 = 16; //RX_PATH_CONTROL:RX_SWITCH_9
|
||||
localparam RX_SWITCH_10_SIZE = 1; //RX_PATH_CONTROL:RX_SWITCH_10
|
||||
localparam RX_SWITCH_10_MSB = 18; //RX_PATH_CONTROL:RX_SWITCH_10
|
||||
localparam RX_SWITCH_10 = 18; //RX_PATH_CONTROL:RX_SWITCH_10
|
||||
localparam RX_SWITCH_11_SIZE = 3; //RX_PATH_CONTROL:RX_SWITCH_11
|
||||
localparam RX_SWITCH_11_MSB = 22; //RX_PATH_CONTROL:RX_SWITCH_11
|
||||
localparam RX_SWITCH_11 = 20; //RX_PATH_CONTROL:RX_SWITCH_11
|
||||
|
||||
// TX_PATH_CONTROL Type (from switch_control.v)
|
||||
localparam TX_PATH_CONTROL_SIZE = 32;
|
||||
localparam TX_PATH_CONTROL_MASK = 32'h53F7FFD;
|
||||
localparam TX_SWITCH_1_2_SIZE = 1; //TX_PATH_CONTROL:TX_SWITCH_1_2
|
||||
localparam TX_SWITCH_1_2_MSB = 0; //TX_PATH_CONTROL:TX_SWITCH_1_2
|
||||
localparam TX_SWITCH_1_2 = 0; //TX_PATH_CONTROL:TX_SWITCH_1_2
|
||||
localparam TX_SWITCH_3_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_3
|
||||
localparam TX_SWITCH_3_MSB = 3; //TX_PATH_CONTROL:TX_SWITCH_3
|
||||
localparam TX_SWITCH_3 = 2; //TX_PATH_CONTROL:TX_SWITCH_3
|
||||
localparam TX_SWITCH_4_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_4
|
||||
localparam TX_SWITCH_4_MSB = 5; //TX_PATH_CONTROL:TX_SWITCH_4
|
||||
localparam TX_SWITCH_4 = 4; //TX_PATH_CONTROL:TX_SWITCH_4
|
||||
localparam TX_SWITCH_5_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_5
|
||||
localparam TX_SWITCH_5_MSB = 7; //TX_PATH_CONTROL:TX_SWITCH_5
|
||||
localparam TX_SWITCH_5 = 6; //TX_PATH_CONTROL:TX_SWITCH_5
|
||||
localparam TX_SWITCH_6_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_6
|
||||
localparam TX_SWITCH_6_MSB = 9; //TX_PATH_CONTROL:TX_SWITCH_6
|
||||
localparam TX_SWITCH_6 = 8; //TX_PATH_CONTROL:TX_SWITCH_6
|
||||
localparam TX_SWITCH_7_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_7
|
||||
localparam TX_SWITCH_7_MSB = 11; //TX_PATH_CONTROL:TX_SWITCH_7
|
||||
localparam TX_SWITCH_7 = 10; //TX_PATH_CONTROL:TX_SWITCH_7
|
||||
localparam TX_SWITCH_8_SIZE = 3; //TX_PATH_CONTROL:TX_SWITCH_8
|
||||
localparam TX_SWITCH_8_MSB = 14; //TX_PATH_CONTROL:TX_SWITCH_8
|
||||
localparam TX_SWITCH_8 = 12; //TX_PATH_CONTROL:TX_SWITCH_8
|
||||
localparam TX_SWITCH_9_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_9
|
||||
localparam TX_SWITCH_9_MSB = 17; //TX_PATH_CONTROL:TX_SWITCH_9
|
||||
localparam TX_SWITCH_9 = 16; //TX_PATH_CONTROL:TX_SWITCH_9
|
||||
localparam TX_SWITCH_10_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_10
|
||||
localparam TX_SWITCH_10_MSB = 19; //TX_PATH_CONTROL:TX_SWITCH_10
|
||||
localparam TX_SWITCH_10 = 18; //TX_PATH_CONTROL:TX_SWITCH_10
|
||||
localparam TX_SWITCH_11_SIZE = 2; //TX_PATH_CONTROL:TX_SWITCH_11
|
||||
localparam TX_SWITCH_11_MSB = 21; //TX_PATH_CONTROL:TX_SWITCH_11
|
||||
localparam TX_SWITCH_11 = 20; //TX_PATH_CONTROL:TX_SWITCH_11
|
||||
localparam TX_SWITCH_13_SIZE = 1; //TX_PATH_CONTROL:TX_SWITCH_13
|
||||
localparam TX_SWITCH_13_MSB = 24; //TX_PATH_CONTROL:TX_SWITCH_13
|
||||
localparam TX_SWITCH_13 = 24; //TX_PATH_CONTROL:TX_SWITCH_13
|
||||
localparam TX_SWITCH_14_SIZE = 1; //TX_PATH_CONTROL:TX_SWITCH_14
|
||||
localparam TX_SWITCH_14_MSB = 26; //TX_PATH_CONTROL:TX_SWITCH_14
|
||||
localparam TX_SWITCH_14 = 26; //TX_PATH_CONTROL:TX_SWITCH_14
|
||||
|
||||
//===============================================================================
|
||||
// Register Group SWITCH_SETUP_REGISTERS
|
||||
//===============================================================================
|
||||
|
||||
// TX0_PATH_CONTROL Register (from switch_control.v)
|
||||
localparam TX0_PATH_CONTROL_COUNT = 256; // Number of elements in array
|
||||
|
||||
// TX1_PATH_CONTROL Register (from switch_control.v)
|
||||
localparam TX1_PATH_CONTROL_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX0_PATH_CONTROL Register (from switch_control.v)
|
||||
localparam RX0_PATH_CONTROL_COUNT = 256; // Number of elements in array
|
||||
|
||||
// RX1_PATH_CONTROL Register (from switch_control.v)
|
||||
localparam RX1_PATH_CONTROL_COUNT = 256; // Number of elements in array
|
||||
|
||||
// Return the offset of an element of register array TX0_PATH_CONTROL
|
||||
function integer TX0_PATH_CONTROL (input integer i);
|
||||
TX0_PATH_CONTROL = (i * 'h4) + 'h0;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array TX1_PATH_CONTROL
|
||||
function integer TX1_PATH_CONTROL (input integer i);
|
||||
TX1_PATH_CONTROL = (i * 'h4) + 'h400;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX0_PATH_CONTROL
|
||||
function integer RX0_PATH_CONTROL (input integer i);
|
||||
RX0_PATH_CONTROL = (i * 'h4) + 'h800;
|
||||
endfunction
|
||||
|
||||
// Return the offset of an element of register array RX1_PATH_CONTROL
|
||||
function integer RX1_PATH_CONTROL (input integer i);
|
||||
RX1_PATH_CONTROL = (i * 'h4) + 'hC00;
|
||||
endfunction
|
||||
@@ -0,0 +1,463 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: zbx_cpld_core
|
||||
//
|
||||
// Description:
|
||||
// Wrapper containing multiple register blocks, each in charge of controlling
|
||||
// different features/signals across the daughterboard. Currently, the following
|
||||
// blocks supported are:
|
||||
// - Scratch/Signature/Revision(Basic Regs) register block
|
||||
// - Led Control block
|
||||
// - TX/RX path switch control block
|
||||
// - TX/RX DSA control block
|
||||
// - Local Oscillator SPI control block
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module zbx_cpld_core #(
|
||||
parameter [19:0] BASE_ADDRESS = 0
|
||||
) (
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// CtrlPort access
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Request
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
|
||||
// Response
|
||||
output wire s_ctrlport_resp_ack,
|
||||
output wire [ 1:0] s_ctrlport_resp_status,
|
||||
output wire [31:0] s_ctrlport_resp_data,
|
||||
|
||||
//reg clk domain
|
||||
input wire ctrlport_clk,
|
||||
input wire ctrlport_rst,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// ATR controls
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
input wire [3:0] atr_fpga_state,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
//// LO SPI signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// LO SPI for LMX2572
|
||||
input wire [7:0] lo_miso,
|
||||
output wire [7:0] lo_csb,
|
||||
|
||||
output wire lo_sclk,
|
||||
output wire lo_mosi,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
//// LO SYNC signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Incoming SYNC
|
||||
input wire mb_synth_sync,
|
||||
|
||||
// SYNC for LMX2572
|
||||
output wire tx0_lo1_sync,
|
||||
output wire tx0_lo2_sync,
|
||||
output wire tx1_lo1_sync,
|
||||
output wire tx1_lo2_sync,
|
||||
output wire rx0_lo1_sync,
|
||||
output wire rx0_lo2_sync,
|
||||
output wire rx1_lo1_sync,
|
||||
output wire rx1_lo2_sync,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
//// TX0 Controls
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Tx0 Switch control
|
||||
output wire tx0_sw1_sw2_ctrl,
|
||||
output wire tx0_sw3_a,
|
||||
output wire tx0_sw3_b,
|
||||
output wire tx0_sw4_a,
|
||||
output wire tx0_sw4_b,
|
||||
output wire tx0_sw5_a,
|
||||
output wire tx0_sw5_b,
|
||||
output wire tx0_sw6_a,
|
||||
output wire tx0_sw6_b,
|
||||
output wire tx0_sw7_a,
|
||||
output wire tx0_sw7_b,
|
||||
output wire tx0_sw8_v1,
|
||||
output wire tx0_sw8_v2,
|
||||
output wire tx0_sw8_v3,
|
||||
output wire tx0_sw9_a,
|
||||
output wire tx0_sw9_b,
|
||||
output wire tx0_sw10_a,
|
||||
output wire tx0_sw10_b,
|
||||
output wire tx0_sw11_a,
|
||||
output wire tx0_sw11_b,
|
||||
output wire tx0_sw13_v1,
|
||||
output wire tx0_sw14_v1,
|
||||
|
||||
//Tx0 DSA control
|
||||
output wire [6:2] tx0_dsa1,
|
||||
output wire [6:2] tx0_dsa2,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
//// TX1 Controls
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Tx1 Switch control
|
||||
output wire tx1_sw1_sw2_ctrl,
|
||||
output wire tx1_sw3_a,
|
||||
output wire tx1_sw3_b,
|
||||
output wire tx1_sw4_a,
|
||||
output wire tx1_sw4_b,
|
||||
output wire tx1_sw5_a,
|
||||
output wire tx1_sw5_b,
|
||||
output wire tx1_sw6_a,
|
||||
output wire tx1_sw6_b,
|
||||
output wire tx1_sw7_a,
|
||||
output wire tx1_sw7_b,
|
||||
output wire tx1_sw8_v1,
|
||||
output wire tx1_sw8_v2,
|
||||
output wire tx1_sw8_v3,
|
||||
output wire tx1_sw9_a,
|
||||
output wire tx1_sw9_b,
|
||||
output wire tx1_sw10_a,
|
||||
output wire tx1_sw10_b,
|
||||
output wire tx1_sw11_a,
|
||||
output wire tx1_sw11_b,
|
||||
output wire tx1_sw13_v1,
|
||||
output wire tx1_sw14_v1,
|
||||
|
||||
//Tx1 DSA control
|
||||
output wire [6:2] tx1_dsa1,
|
||||
output wire [6:2] tx1_dsa2,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
//// RX0 Controls
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Rx0 Switch control
|
||||
output wire rx0_sw1_a,
|
||||
output wire rx0_sw1_b,
|
||||
output wire rx0_sw2_a,
|
||||
output wire rx0_sw3_v1,
|
||||
output wire rx0_sw3_v2,
|
||||
output wire rx0_sw3_v3,
|
||||
output wire rx0_sw4_a,
|
||||
output wire rx0_sw5_a,
|
||||
output wire rx0_sw5_b,
|
||||
output wire rx0_sw6_a,
|
||||
output wire rx0_sw6_b,
|
||||
output wire rx0_sw7_sw8_ctrl,
|
||||
output wire rx0_sw9_v1,
|
||||
output wire rx0_sw10_v1,
|
||||
output wire rx0_sw11_v3,
|
||||
output wire rx0_sw11_v2,
|
||||
output wire rx0_sw11_v1,
|
||||
|
||||
//Rx0 DSA control
|
||||
output wire [1:4] rx0_dsa1_n,
|
||||
output wire [1:4] rx0_dsa2_n,
|
||||
output wire [1:4] rx0_dsa3_a_n,
|
||||
output wire [1:4] rx0_dsa3_b_n,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
//// RX1 Controls
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//Rx1 Switch Control
|
||||
output wire rx1_sw1_a,
|
||||
output wire rx1_sw1_b,
|
||||
output wire rx1_sw2_a,
|
||||
output wire rx1_sw3_v1,
|
||||
output wire rx1_sw3_v2,
|
||||
output wire rx1_sw3_v3,
|
||||
output wire rx1_sw4_a,
|
||||
output wire rx1_sw5_a,
|
||||
output wire rx1_sw5_b,
|
||||
output wire rx1_sw6_a,
|
||||
output wire rx1_sw6_b,
|
||||
output wire rx1_sw7_sw8_ctrl,
|
||||
output wire rx1_sw9_v1,
|
||||
output wire rx1_sw10_v1,
|
||||
output wire rx1_sw11_v3,
|
||||
output wire rx1_sw11_v2,
|
||||
output wire rx1_sw11_v1,
|
||||
|
||||
//Rx1 DSA control
|
||||
output wire [1:4] rx1_dsa1_n,
|
||||
output wire [1:4] rx1_dsa2_n,
|
||||
output wire [1:4] rx1_dsa3_a_n,
|
||||
output wire [1:4] rx1_dsa3_b_n,
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// LED Control
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
output wire ch0_rx2_led,
|
||||
output wire ch0_tx_led,
|
||||
output wire ch0_rx_led,
|
||||
output wire ch1_rx2_led,
|
||||
output wire ch1_tx_led,
|
||||
output wire ch1_rx_led
|
||||
|
||||
);
|
||||
|
||||
`include "regmap/db_control_regmap_utils.vh"
|
||||
`include "../../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
|
||||
// internal ATR configuration
|
||||
wire [7:0] atr_config_rf0;
|
||||
wire [7:0] atr_config_rf1;
|
||||
wire [7:0] atr_config_dsa_rf0;
|
||||
wire [7:0] atr_config_dsa_rf1;
|
||||
|
||||
// Master Interfaces
|
||||
wire [ REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_wr;
|
||||
wire [ REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_rd;
|
||||
wire [CTRLPORT_ADDR_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_addr;
|
||||
wire [CTRLPORT_DATA_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_req_data;
|
||||
wire [ REGISTER_BLOCKS_SIZE-1:0] ctrlport_resp_ack;
|
||||
wire [ CTRLPORT_STS_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_resp_status;
|
||||
wire [CTRLPORT_DATA_W*REGISTER_BLOCKS_SIZE-1:0] ctrlport_resp_data;
|
||||
|
||||
ctrlport_splitter #(
|
||||
.NUM_SLAVES(REGISTER_BLOCKS_SIZE)
|
||||
) ctrlport_splitter_i (
|
||||
.ctrlport_clk (ctrlport_clk),
|
||||
.ctrlport_rst (ctrlport_rst),
|
||||
.s_ctrlport_req_wr (s_ctrlport_req_wr),
|
||||
.s_ctrlport_req_rd (s_ctrlport_req_rd),
|
||||
.s_ctrlport_req_addr (s_ctrlport_req_addr),
|
||||
.s_ctrlport_req_data (s_ctrlport_req_data),
|
||||
.s_ctrlport_req_byte_en (),
|
||||
.s_ctrlport_req_has_time (),
|
||||
.s_ctrlport_req_time (),
|
||||
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
|
||||
.s_ctrlport_resp_status (s_ctrlport_resp_status),
|
||||
.s_ctrlport_resp_data (s_ctrlport_resp_data),
|
||||
.m_ctrlport_req_wr (ctrlport_req_wr),
|
||||
.m_ctrlport_req_rd (ctrlport_req_rd),
|
||||
.m_ctrlport_req_addr (ctrlport_req_addr),
|
||||
.m_ctrlport_req_data (ctrlport_req_data),
|
||||
.m_ctrlport_req_byte_en (),
|
||||
.m_ctrlport_req_has_time (),
|
||||
.m_ctrlport_req_time (),
|
||||
.m_ctrlport_resp_ack (ctrlport_resp_ack),
|
||||
.m_ctrlport_resp_status (ctrlport_resp_status),
|
||||
.m_ctrlport_resp_data (ctrlport_resp_data)
|
||||
);
|
||||
|
||||
atr_controller #(
|
||||
.BASE_ADDRESS (ATR_CONTROLLER_REGS + BASE_ADDRESS),
|
||||
.SIZE_ADDRESS (ATR_CONTROLLER_REGS_SIZE)
|
||||
) atr_controller_i (
|
||||
.ctrlport_clk (ctrlport_clk),
|
||||
.ctrlport_rst (ctrlport_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_req_wr[ATR_REGISTERS]),
|
||||
.s_ctrlport_req_rd (ctrlport_req_rd[ATR_REGISTERS]),
|
||||
.s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(ATR_REGISTERS) +: CTRLPORT_ADDR_W]),
|
||||
.s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(ATR_REGISTERS) +: CTRLPORT_DATA_W]),
|
||||
.s_ctrlport_resp_ack (ctrlport_resp_ack[ATR_REGISTERS]),
|
||||
.s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(ATR_REGISTERS) +: CTRLPORT_STS_W]),
|
||||
.s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(ATR_REGISTERS) +: CTRLPORT_DATA_W]),
|
||||
.atr_fpga_state (atr_fpga_state),
|
||||
.atr_config_dsa_rf0 (atr_config_dsa_rf0),
|
||||
.atr_config_dsa_rf1 (atr_config_dsa_rf1),
|
||||
.atr_config_rf0 (atr_config_rf0),
|
||||
.atr_config_rf1 (atr_config_rf1)
|
||||
);
|
||||
|
||||
switch_control #(
|
||||
.BASE_ADDRESS (SWITCH_SETUP_REGS + BASE_ADDRESS),
|
||||
.SIZE_ADDRESS (SWITCH_SETUP_REGS_SIZE)
|
||||
) switch_control_i (
|
||||
.ctrlport_clk (ctrlport_clk),
|
||||
.ctrlport_rst (ctrlport_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_req_wr[SW_CONTROL]),
|
||||
.s_ctrlport_req_rd (ctrlport_req_rd[SW_CONTROL]),
|
||||
.s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(SW_CONTROL) +: CTRLPORT_ADDR_W]),
|
||||
.s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(SW_CONTROL) +: CTRLPORT_DATA_W]),
|
||||
.s_ctrlport_resp_ack (ctrlport_resp_ack[SW_CONTROL]),
|
||||
.s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(SW_CONTROL) +: CTRLPORT_STS_W]),
|
||||
.s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(SW_CONTROL) +: CTRLPORT_DATA_W]),
|
||||
.atr_config_rf0 (atr_config_rf0),
|
||||
.atr_config_rf1 (atr_config_rf1),
|
||||
.tx0_sw1_sw2_ctrl (tx0_sw1_sw2_ctrl),
|
||||
.tx0_sw3_a (tx0_sw3_a),
|
||||
.tx0_sw3_b (tx0_sw3_b),
|
||||
.tx0_sw4_a (tx0_sw4_a),
|
||||
.tx0_sw4_b (tx0_sw4_b),
|
||||
.tx0_sw5_a (tx0_sw5_a),
|
||||
.tx0_sw5_b (tx0_sw5_b),
|
||||
.tx0_sw6_a (tx0_sw6_a),
|
||||
.tx0_sw6_b (tx0_sw6_b),
|
||||
.tx0_sw7_a (tx0_sw7_a),
|
||||
.tx0_sw7_b (tx0_sw7_b),
|
||||
.tx0_sw8_v1 (tx0_sw8_v1),
|
||||
.tx0_sw8_v2 (tx0_sw8_v2),
|
||||
.tx0_sw8_v3 (tx0_sw8_v3),
|
||||
.tx0_sw9_a (tx0_sw9_a),
|
||||
.tx0_sw9_b (tx0_sw9_b),
|
||||
.tx0_sw10_a (tx0_sw10_a),
|
||||
.tx0_sw10_b (tx0_sw10_b),
|
||||
.tx0_sw11_a (tx0_sw11_a),
|
||||
.tx0_sw11_b (tx0_sw11_b),
|
||||
.tx0_sw13_v1 (tx0_sw13_v1),
|
||||
.tx0_sw14_v1 (tx0_sw14_v1),
|
||||
.tx1_sw1_sw2_ctrl (tx1_sw1_sw2_ctrl),
|
||||
.tx1_sw3_a (tx1_sw3_a),
|
||||
.tx1_sw3_b (tx1_sw3_b),
|
||||
.tx1_sw4_a (tx1_sw4_a),
|
||||
.tx1_sw4_b (tx1_sw4_b),
|
||||
.tx1_sw5_a (tx1_sw5_a),
|
||||
.tx1_sw5_b (tx1_sw5_b),
|
||||
.tx1_sw6_a (tx1_sw6_a),
|
||||
.tx1_sw6_b (tx1_sw6_b),
|
||||
.tx1_sw7_a (tx1_sw7_a),
|
||||
.tx1_sw7_b (tx1_sw7_b),
|
||||
.tx1_sw8_v1 (tx1_sw8_v1),
|
||||
.tx1_sw8_v2 (tx1_sw8_v2),
|
||||
.tx1_sw8_v3 (tx1_sw8_v3),
|
||||
.tx1_sw9_a (tx1_sw9_a),
|
||||
.tx1_sw9_b (tx1_sw9_b),
|
||||
.tx1_sw10_a (tx1_sw10_a),
|
||||
.tx1_sw10_b (tx1_sw10_b),
|
||||
.tx1_sw11_a (tx1_sw11_a),
|
||||
.tx1_sw11_b (tx1_sw11_b),
|
||||
.tx1_sw13_v1 (tx1_sw13_v1),
|
||||
.tx1_sw14_v1 (tx1_sw14_v1),
|
||||
.rx0_sw1_a (rx0_sw1_a),
|
||||
.rx0_sw1_b (rx0_sw1_b),
|
||||
.rx0_sw2_a (rx0_sw2_a),
|
||||
.rx0_sw3_v1 (rx0_sw3_v1),
|
||||
.rx0_sw3_v2 (rx0_sw3_v2),
|
||||
.rx0_sw3_v3 (rx0_sw3_v3),
|
||||
.rx0_sw4_a (rx0_sw4_a),
|
||||
.rx0_sw5_a (rx0_sw5_a),
|
||||
.rx0_sw5_b (rx0_sw5_b),
|
||||
.rx0_sw6_a (rx0_sw6_a),
|
||||
.rx0_sw6_b (rx0_sw6_b),
|
||||
.rx0_sw7_sw8_ctrl (rx0_sw7_sw8_ctrl),
|
||||
.rx0_sw9_v1 (rx0_sw9_v1),
|
||||
.rx0_sw10_v1 (rx0_sw10_v1),
|
||||
.rx0_sw11_v3 (rx0_sw11_v3),
|
||||
.rx0_sw11_v2 (rx0_sw11_v2),
|
||||
.rx0_sw11_v1 (rx0_sw11_v1),
|
||||
.rx1_sw1_a (rx1_sw1_a),
|
||||
.rx1_sw1_b (rx1_sw1_b),
|
||||
.rx1_sw2_a (rx1_sw2_a),
|
||||
.rx1_sw3_v1 (rx1_sw3_v1),
|
||||
.rx1_sw3_v2 (rx1_sw3_v2),
|
||||
.rx1_sw3_v3 (rx1_sw3_v3),
|
||||
.rx1_sw4_a (rx1_sw4_a),
|
||||
.rx1_sw5_a (rx1_sw5_a),
|
||||
.rx1_sw5_b (rx1_sw5_b),
|
||||
.rx1_sw6_a (rx1_sw6_a),
|
||||
.rx1_sw6_b (rx1_sw6_b),
|
||||
.rx1_sw7_sw8_ctrl (rx1_sw7_sw8_ctrl),
|
||||
.rx1_sw9_v1 (rx1_sw9_v1),
|
||||
.rx1_sw10_v1 (rx1_sw10_v1),
|
||||
.rx1_sw11_v3 (rx1_sw11_v3),
|
||||
.rx1_sw11_v2 (rx1_sw11_v2),
|
||||
.rx1_sw11_v1 (rx1_sw11_v1)
|
||||
);
|
||||
|
||||
dsa_control #(
|
||||
.BASE_ADDRESS (DSA_SETUP_REGS + BASE_ADDRESS),
|
||||
.SIZE_ADDRESS (DSA_SETUP_REGS_SIZE)
|
||||
) dsa_control_i (
|
||||
.ctrlport_clk (ctrlport_clk),
|
||||
.ctrlport_rst (ctrlport_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_req_wr[DSA_CONTROL]),
|
||||
.s_ctrlport_req_rd (ctrlport_req_rd[DSA_CONTROL]),
|
||||
.s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(DSA_CONTROL) +:CTRLPORT_ADDR_W]),
|
||||
.s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(DSA_CONTROL) +:CTRLPORT_DATA_W]),
|
||||
.s_ctrlport_resp_ack (ctrlport_resp_ack[DSA_CONTROL]),
|
||||
.s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(DSA_CONTROL) +:CTRLPORT_STS_W]),
|
||||
.s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(DSA_CONTROL) +:CTRLPORT_DATA_W]),
|
||||
.atr_config_rf0 (atr_config_dsa_rf0),
|
||||
.atr_config_rf1 (atr_config_dsa_rf1),
|
||||
.tx0_dsa1 (tx0_dsa1),
|
||||
.tx0_dsa2 (tx0_dsa2),
|
||||
.tx1_dsa1 (tx1_dsa1),
|
||||
.tx1_dsa2 (tx1_dsa2),
|
||||
.rx0_dsa1_n (rx0_dsa1_n),
|
||||
.rx0_dsa2_n (rx0_dsa2_n),
|
||||
.rx0_dsa3_a_n (rx0_dsa3_a_n),
|
||||
.rx0_dsa3_b_n (rx0_dsa3_b_n),
|
||||
.rx1_dsa1_n (rx1_dsa1_n),
|
||||
.rx1_dsa2_n (rx1_dsa2_n),
|
||||
.rx1_dsa3_a_n (rx1_dsa3_a_n),
|
||||
.rx1_dsa3_b_n (rx1_dsa3_b_n)
|
||||
);
|
||||
|
||||
led_control #(
|
||||
.BASE_ADDRESS (LED_SETUP_REGS + BASE_ADDRESS),
|
||||
.SIZE_ADDRESS (LED_SETUP_REGS_SIZE)
|
||||
) led_control_i (
|
||||
.ctrlport_clk (ctrlport_clk),
|
||||
.ctrlport_rst (ctrlport_rst),
|
||||
.s_ctrlport_req_wr (ctrlport_req_wr[LED_REGISTERS]),
|
||||
.s_ctrlport_req_rd (ctrlport_req_rd[LED_REGISTERS]),
|
||||
.s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(LED_REGISTERS) +: CTRLPORT_ADDR_W]),
|
||||
.s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(LED_REGISTERS) +: CTRLPORT_DATA_W]),
|
||||
.s_ctrlport_resp_ack (ctrlport_resp_ack[LED_REGISTERS]),
|
||||
.s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(LED_REGISTERS) +: CTRLPORT_STS_W]),
|
||||
.s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(LED_REGISTERS) +: CTRLPORT_DATA_W]),
|
||||
.ch0_rx2_led (ch0_rx2_led),
|
||||
.ch0_tx_led (ch0_tx_led),
|
||||
.ch0_rx_led (ch0_rx_led),
|
||||
.ch1_rx2_led (ch1_rx2_led),
|
||||
.ch1_tx_led (ch1_tx_led),
|
||||
.ch1_rx_led (ch1_rx_led),
|
||||
.atr_config_rf0 (atr_config_rf0),
|
||||
.atr_config_rf1 (atr_config_rf1)
|
||||
);
|
||||
|
||||
lo_control #(
|
||||
.BASE_ADDRESS (LO_CONTROL_REGS + BASE_ADDRESS),
|
||||
.SIZE_ADDRESS (LO_CONTROL_REGS_SIZE)
|
||||
) lo_control_i (
|
||||
.s_ctrlport_req_wr (ctrlport_req_wr[LO_SPI]),
|
||||
.s_ctrlport_req_rd (ctrlport_req_rd[LO_SPI]),
|
||||
.s_ctrlport_req_addr (ctrlport_req_addr[CTRLPORT_ADDR_W*(LO_SPI) +: CTRLPORT_ADDR_W]),
|
||||
.s_ctrlport_req_data (ctrlport_req_data[CTRLPORT_DATA_W*(LO_SPI) +: CTRLPORT_DATA_W]),
|
||||
.s_ctrlport_resp_ack (ctrlport_resp_ack[LO_SPI]),
|
||||
.s_ctrlport_resp_status (ctrlport_resp_status[CTRLPORT_STS_W*(LO_SPI) +: CTRLPORT_STS_W]),
|
||||
.s_ctrlport_resp_data (ctrlport_resp_data[CTRLPORT_DATA_W*(LO_SPI) +: CTRLPORT_DATA_W]),
|
||||
.ctrlport_clk (ctrlport_clk),
|
||||
.ctrlport_rst (ctrlport_rst),
|
||||
.miso (lo_miso),
|
||||
.ss (lo_csb),
|
||||
.sclk (lo_sclk),
|
||||
.mosi (lo_mosi),
|
||||
.mb_synth_sync (mb_synth_sync),
|
||||
.tx0_lo1_sync (tx0_lo1_sync),
|
||||
.tx0_lo2_sync (tx0_lo2_sync),
|
||||
.tx1_lo1_sync (tx1_lo1_sync),
|
||||
.tx1_lo2_sync (tx1_lo2_sync),
|
||||
.rx0_lo1_sync (rx0_lo1_sync),
|
||||
.rx0_lo2_sync (rx0_lo2_sync),
|
||||
.rx1_lo1_sync (rx1_lo1_sync),
|
||||
.rx1_lo2_sync (rx1_lo2_sync));
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="DB_CONTROL_REGMAP" readablestrobes="false" generatevhdl="true">
|
||||
// <group name="REGISTER_ENDPOINTS" offset="0x000" size="0x000">
|
||||
// <enumeratedtype name="REGISTER_BLOCKS">
|
||||
// <value name="ATR_REGISTERS" integer="0"/>
|
||||
// <value name="LED_REGISTERS" integer="1"/>
|
||||
// <value name="LO_SPI" integer="2"/>
|
||||
// <value name="SW_CONTROL" integer="3"/>
|
||||
// <value name="DSA_CONTROL" integer="4"/>
|
||||
// </enumeratedtype>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
|
||||
# Date created = 17:19:38 August 16, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "17.1"
|
||||
DATE = "17:19:38 August 16, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "zbx_top_cpld"
|
||||
@@ -0,0 +1,889 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2017 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
|
||||
# Date created = 15:10:13 February 02, 2018
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# TopCpld_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "MAX 10"
|
||||
|
||||
# Device that is being used in production run
|
||||
set_global_assignment -name DEVICE 10M04SAU324I7G
|
||||
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:10:13 FEBRUARY 02, 2018"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
|
||||
set_global_assignment -name GENERATE_SVF_FILE OFF
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
|
||||
|
||||
set_location_assignment PIN_P2 -to CTRL_REG_ARST
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_ARST
|
||||
|
||||
set_location_assignment PIN_M4 -to CTRL_REG_CLK
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to CTRL_REG_CLK
|
||||
|
||||
set_location_assignment PIN_N1 -to MB_CTRL_CS
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_CS
|
||||
|
||||
set_location_assignment PIN_U2 -to MB_CTRL_MISO
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MISO
|
||||
|
||||
set_location_assignment PIN_N3 -to MB_CTRL_MOSI
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_MOSI
|
||||
|
||||
set_location_assignment PIN_L3 -to MB_CTRL_SCK
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_CTRL_SCK
|
||||
|
||||
# The digital daughterboard connector has 120 pins [A-F][1-20].
|
||||
# The assignment below orders the CPLD IOs MSB first and connects it to the DB
|
||||
# connection with increasing letter and increasing number.
|
||||
# This results in:
|
||||
# FPGA Bit 13 = A14 (trace: MB_FPGA_GPIO_A14)
|
||||
# FPGA Bit 12 = A16 (trace: MB_FPGA_GPIO_A16)
|
||||
# ...
|
||||
# FPGA Bit 0 = C19 (trace: MB_FPGA_GPIO_C19)
|
||||
set_location_assignment PIN_R2 -to MB_FPGA_GPIO[13]
|
||||
# Workaround for missing pull down resistor:
|
||||
# Use pull up and schmitt trigger to detect FPGA reload by line going high unexpectedly
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V SCHMITT TRIGGER" -to MB_FPGA_GPIO[13]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MB_FPGA_GPIO[13]
|
||||
|
||||
set_location_assignment PIN_N4 -to MB_FPGA_GPIO[12]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[12]
|
||||
|
||||
set_location_assignment PIN_K8 -to MB_FPGA_GPIO[11]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[11]
|
||||
|
||||
set_location_assignment PIN_M2 -to MB_FPGA_GPIO[10]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[10]
|
||||
|
||||
set_location_assignment PIN_M1 -to MB_FPGA_GPIO[9]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[9]
|
||||
|
||||
set_location_assignment PIN_T1 -to MB_FPGA_GPIO[8]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[8]
|
||||
|
||||
set_location_assignment PIN_U1 -to MB_FPGA_GPIO[7]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[7]
|
||||
|
||||
set_location_assignment PIN_P1 -to MB_FPGA_GPIO[6]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[6]
|
||||
|
||||
set_location_assignment PIN_R3 -to MB_FPGA_GPIO[5]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[5]
|
||||
|
||||
set_location_assignment PIN_M7 -to MB_FPGA_GPIO[4]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[4]
|
||||
|
||||
set_location_assignment PIN_T3 -to MB_FPGA_GPIO[3]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[3]
|
||||
|
||||
set_location_assignment PIN_P4 -to MB_FPGA_GPIO[2]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[2]
|
||||
|
||||
set_location_assignment PIN_L7 -to MB_FPGA_GPIO[1]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[1]
|
||||
|
||||
set_location_assignment PIN_L8 -to MB_FPGA_GPIO[0]
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_FPGA_GPIO[0]
|
||||
|
||||
set_location_assignment PIN_M3 -to MB_SYNTH_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "1.8 V" -to MB_SYNTH_SYNC
|
||||
|
||||
set_location_assignment PIN_G18 -to RX0_LO1_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_CSB
|
||||
|
||||
set_location_assignment PIN_J18 -to RX0_LO1_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SCK
|
||||
|
||||
set_location_assignment PIN_F16 -to RX0_LO1_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SDI
|
||||
|
||||
set_location_assignment PIN_H17 -to RX0_LO1_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_SYNC
|
||||
|
||||
set_location_assignment PIN_J12 -to RX0_LO2_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_CSB
|
||||
|
||||
set_location_assignment PIN_J15 -to RX0_LO2_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SCK
|
||||
|
||||
set_location_assignment PIN_J16 -to RX0_LO2_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SDI
|
||||
|
||||
set_location_assignment PIN_K18 -to RX0_LO2_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_SYNC
|
||||
|
||||
set_location_assignment PIN_F15 -to RX1_LO1_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_CSB
|
||||
|
||||
set_location_assignment PIN_K17 -to RX1_LO1_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SCK
|
||||
|
||||
set_location_assignment PIN_G15 -to RX1_LO1_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SDI
|
||||
|
||||
set_location_assignment PIN_H18 -to RX1_LO1_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_SYNC
|
||||
|
||||
set_location_assignment PIN_H15 -to RX1_LO2_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_CSB
|
||||
|
||||
set_location_assignment PIN_L17 -to RX1_LO2_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SCK
|
||||
|
||||
set_location_assignment PIN_M17 -to RX1_LO2_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SDI
|
||||
|
||||
set_location_assignment PIN_L18 -to RX1_LO2_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_SYNC
|
||||
|
||||
set_location_assignment PIN_C18 -to TX0_LO1_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_CSB
|
||||
|
||||
set_location_assignment PIN_H12 -to TX0_LO1_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SCK
|
||||
|
||||
set_location_assignment PIN_D15 -to TX0_LO1_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SDI
|
||||
|
||||
set_location_assignment PIN_E15 -to TX0_LO1_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_SYNC
|
||||
|
||||
set_location_assignment PIN_E18 -to TX0_LO2_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_CSB
|
||||
|
||||
set_location_assignment PIN_G17 -to TX0_LO2_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SCK
|
||||
|
||||
set_location_assignment PIN_C17 -to TX0_LO2_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SDI
|
||||
|
||||
set_location_assignment PIN_D17 -to TX0_LO2_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_SYNC
|
||||
|
||||
set_location_assignment PIN_G11 -to TX1_LO1_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_CSB
|
||||
|
||||
set_location_assignment PIN_D16 -to TX1_LO1_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SCK
|
||||
|
||||
set_location_assignment PIN_E16 -to TX1_LO1_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SDI
|
||||
|
||||
set_location_assignment PIN_B18 -to TX1_LO1_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_SYNC
|
||||
|
||||
set_location_assignment PIN_E17 -to TX1_LO2_CSB
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_CSB
|
||||
|
||||
set_location_assignment PIN_G16 -to TX1_LO2_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SCK
|
||||
|
||||
set_location_assignment PIN_D18 -to TX1_LO2_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SDI
|
||||
|
||||
set_location_assignment PIN_H16 -to TX1_LO2_SYNC
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_SYNC
|
||||
|
||||
set_location_assignment PIN_M12 -to RX0_DSA3_A_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[1]
|
||||
|
||||
set_location_assignment PIN_T16 -to RX0_DSA3_A_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[2]
|
||||
|
||||
set_location_assignment PIN_N15 -to RX0_DSA3_A_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[3]
|
||||
|
||||
set_location_assignment PIN_M15 -to RX0_DSA3_A_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_A_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_A_n[4]
|
||||
|
||||
set_location_assignment PIN_L12 -to RX1_DSA3_A_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[1]
|
||||
|
||||
set_location_assignment PIN_L15 -to RX1_DSA3_A_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[2]
|
||||
|
||||
set_location_assignment PIN_L16 -to RX1_DSA3_A_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[3]
|
||||
|
||||
set_location_assignment PIN_K15 -to RX1_DSA3_A_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_A_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_A_n[4]
|
||||
|
||||
set_location_assignment PIN_R18 -to P7V_PG_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_A
|
||||
|
||||
set_location_assignment PIN_N18 -to P7V_PG_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_PG_B
|
||||
|
||||
set_location_assignment PIN_K12 -to CPLD_REFCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPLD_REFCLK
|
||||
|
||||
set_location_assignment PIN_R16 -to P3D3VA_ENABLE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P3D3VA_ENABLE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P3D3VA_ENABLE
|
||||
|
||||
set_location_assignment PIN_P16 -to P7V_ENABLE_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_A
|
||||
|
||||
set_location_assignment PIN_R17 -to P7V_ENABLE_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P7V_ENABLE_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to P7V_ENABLE_B
|
||||
|
||||
set_location_assignment PIN_H6 -to RX0_DSA1_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[1]
|
||||
|
||||
set_location_assignment PIN_J3 -to RX0_DSA1_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[2]
|
||||
|
||||
set_location_assignment PIN_J4 -to RX0_DSA1_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[3]
|
||||
|
||||
set_location_assignment PIN_K4 -to RX0_DSA1_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA1_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA1_n[4]
|
||||
|
||||
set_location_assignment PIN_T4 -to RX0_DSA2_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[1]
|
||||
|
||||
set_location_assignment PIN_N8 -to RX0_DSA2_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[2]
|
||||
|
||||
set_location_assignment PIN_T5 -to RX0_DSA2_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[3]
|
||||
|
||||
set_location_assignment PIN_T6 -to RX0_DSA2_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA2_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA2_n[4]
|
||||
|
||||
set_location_assignment PIN_V2 -to RX0_DSA3_B_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[1]
|
||||
|
||||
set_location_assignment PIN_U5 -to RX0_DSA3_B_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[2]
|
||||
|
||||
set_location_assignment PIN_V5 -to RX0_DSA3_B_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[3]
|
||||
|
||||
set_location_assignment PIN_V6 -to RX0_DSA3_B_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_DSA3_B_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_DSA3_B_n[4]
|
||||
|
||||
set_location_assignment PIN_T15 -to RX0_LO1_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO1_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO1_MUXOUT
|
||||
|
||||
set_location_assignment PIN_T14 -to RX0_LO2_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_LO2_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_LO2_MUXOUT
|
||||
|
||||
set_location_assignment PIN_U8 -to RX0_SW1_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_A
|
||||
|
||||
set_location_assignment PIN_V8 -to RX0_SW1_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW1_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW1_B
|
||||
|
||||
set_location_assignment PIN_T12 -to RX0_SW10_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW10_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW10_V1
|
||||
|
||||
set_location_assignment PIN_P10 -to RX0_SW11_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V1
|
||||
|
||||
set_location_assignment PIN_U17 -to RX0_SW11_V2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V2
|
||||
|
||||
set_location_assignment PIN_F5 -to RX0_SW11_V3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW11_V3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW11_V3
|
||||
|
||||
set_location_assignment PIN_R8 -to RX0_SW2_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW2_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW2_A
|
||||
|
||||
set_location_assignment PIN_U15 -to RX0_SW3_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V1
|
||||
|
||||
set_location_assignment PIN_P14 -to RX0_SW3_V2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V2
|
||||
|
||||
set_location_assignment PIN_T11 -to RX0_SW3_V3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW3_V3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW3_V3
|
||||
|
||||
set_location_assignment PIN_L11 -to RX0_SW4_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW4_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW4_A
|
||||
|
||||
set_location_assignment PIN_P5 -to RX0_SW5_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_A
|
||||
|
||||
set_location_assignment PIN_N7 -to RX0_SW5_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW5_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW5_B
|
||||
|
||||
set_location_assignment PIN_U13 -to RX0_SW6_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_A
|
||||
|
||||
set_location_assignment PIN_V10 -to RX0_SW6_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW6_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW6_B
|
||||
|
||||
set_location_assignment PIN_D13 -to RX0_SW7_SW8_CTRL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW7_SW8_CTRL
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW7_SW8_CTRL
|
||||
|
||||
set_location_assignment PIN_R15 -to RX0_SW9_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX0_SW9_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX0_SW9_V1
|
||||
|
||||
set_location_assignment PIN_R9 -to RX1_DSA1_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[1]
|
||||
|
||||
set_location_assignment PIN_P6 -to RX1_DSA1_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[2]
|
||||
|
||||
set_location_assignment PIN_R6 -to RX1_DSA1_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[3]
|
||||
|
||||
set_location_assignment PIN_M10 -to RX1_DSA1_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA1_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA1_n[4]
|
||||
|
||||
set_location_assignment PIN_T7 -to RX1_DSA2_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[1]
|
||||
|
||||
set_location_assignment PIN_M9 -to RX1_DSA2_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[2]
|
||||
|
||||
set_location_assignment PIN_R5 -to RX1_DSA2_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[3]
|
||||
|
||||
set_location_assignment PIN_R4 -to RX1_DSA2_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA2_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA2_n[4]
|
||||
|
||||
set_location_assignment PIN_U6 -to RX1_DSA3_B_n[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[1]
|
||||
|
||||
set_location_assignment PIN_V4 -to RX1_DSA3_B_n[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[2]
|
||||
|
||||
set_location_assignment PIN_V3 -to RX1_DSA3_B_n[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[3]
|
||||
|
||||
set_location_assignment PIN_U3 -to RX1_DSA3_B_n[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_DSA3_B_n[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_DSA3_B_n[4]
|
||||
|
||||
set_location_assignment PIN_P15 -to RX1_LO1_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO1_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO1_MUXOUT
|
||||
|
||||
set_location_assignment PIN_R14 -to RX1_LO2_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_LO2_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_LO2_MUXOUT
|
||||
|
||||
set_location_assignment PIN_D7 -to RX1_SW1_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_A
|
||||
|
||||
set_location_assignment PIN_D8 -to RX1_SW1_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW1_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW1_B
|
||||
|
||||
set_location_assignment PIN_R12 -to RX1_SW10_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW10_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW10_V1
|
||||
|
||||
set_location_assignment PIN_V17 -to RX1_SW11_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V1
|
||||
|
||||
set_location_assignment PIN_R10 -to RX1_SW11_V2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V2
|
||||
|
||||
set_location_assignment PIN_F2 -to RX1_SW11_V3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW11_V3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW11_V3
|
||||
|
||||
set_location_assignment PIN_T8 -to RX1_SW2_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW2_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW2_A
|
||||
|
||||
set_location_assignment PIN_T10 -to RX1_SW3_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V1
|
||||
|
||||
set_location_assignment PIN_V16 -to RX1_SW3_V2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V2
|
||||
|
||||
set_location_assignment PIN_U16 -to RX1_SW3_V3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW3_V3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW3_V3
|
||||
|
||||
set_location_assignment PIN_K7 -to RX1_SW4_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW4_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW4_A
|
||||
|
||||
set_location_assignment PIN_M11 -to RX1_SW5_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_A
|
||||
|
||||
set_location_assignment PIN_M8 -to RX1_SW5_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW5_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW5_B
|
||||
|
||||
set_location_assignment PIN_U9 -to RX1_SW6_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_A
|
||||
|
||||
set_location_assignment PIN_V9 -to RX1_SW6_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW6_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW6_B
|
||||
|
||||
set_location_assignment PIN_E14 -to RX1_SW7_SW8_CTRL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW7_SW8_CTRL
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW7_SW8_CTRL
|
||||
|
||||
set_location_assignment PIN_N14 -to RX1_SW9_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RX1_SW9_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to RX1_SW9_V1
|
||||
|
||||
set_location_assignment PIN_C13 -to TX0_DSA1[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[2]
|
||||
|
||||
set_location_assignment PIN_D14 -to TX0_DSA1[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[3]
|
||||
|
||||
set_location_assignment PIN_A15 -to TX0_DSA1[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[4]
|
||||
|
||||
set_location_assignment PIN_B14 -to TX0_DSA1[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[5]
|
||||
|
||||
set_location_assignment PIN_C16 -to TX0_DSA1[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA1[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA1[6]
|
||||
|
||||
set_location_assignment PIN_A2 -to TX0_DSA2[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[2]
|
||||
|
||||
set_location_assignment PIN_C5 -to TX0_DSA2[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[3]
|
||||
|
||||
set_location_assignment PIN_C4 -to TX0_DSA2[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[4]
|
||||
|
||||
set_location_assignment PIN_D10 -to TX0_DSA2[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[5]
|
||||
|
||||
set_location_assignment PIN_B2 -to TX0_DSA2[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_DSA2[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_DSA2[6]
|
||||
|
||||
set_location_assignment PIN_A8 -to TX0_LO1_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO1_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO1_MUXOUT
|
||||
|
||||
set_location_assignment PIN_F12 -to TX0_LO2_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_LO2_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_LO2_MUXOUT
|
||||
|
||||
set_location_assignment PIN_A14 -to TX0_SW1_SW2_CTRL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW1_SW2_CTRL
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW1_SW2_CTRL
|
||||
|
||||
set_location_assignment PIN_U7 -to TX0_SW10_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_A
|
||||
|
||||
set_location_assignment PIN_V7 -to TX0_SW10_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW10_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW10_B
|
||||
|
||||
set_location_assignment PIN_V15 -to TX0_SW11_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_A
|
||||
|
||||
set_location_assignment PIN_V14 -to TX0_SW11_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW11_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW11_B
|
||||
|
||||
set_location_assignment PIN_F11 -to TX0_SW13_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW13_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW13_V1
|
||||
|
||||
set_location_assignment PIN_B9 -to TX0_SW14_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW14_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW14_V1
|
||||
|
||||
set_location_assignment PIN_E4 -to TX0_SW3_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_A
|
||||
|
||||
set_location_assignment PIN_D1 -to TX0_SW3_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW3_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW3_B
|
||||
|
||||
set_location_assignment PIN_J1 -to TX0_SW4_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_A
|
||||
|
||||
set_location_assignment PIN_H2 -to TX0_SW4_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW4_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW4_B
|
||||
|
||||
set_location_assignment PIN_K3 -to TX0_SW5_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_A
|
||||
|
||||
set_location_assignment PIN_L2 -to TX0_SW5_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW5_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW5_B
|
||||
|
||||
set_location_assignment PIN_G1 -to TX0_SW6_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_A
|
||||
|
||||
set_location_assignment PIN_G3 -to TX0_SW6_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW6_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW6_B
|
||||
|
||||
set_location_assignment PIN_C1 -to TX0_SW7_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_A
|
||||
|
||||
set_location_assignment PIN_D4 -to TX0_SW7_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW7_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW7_B
|
||||
|
||||
set_location_assignment PIN_C8 -to TX0_SW8_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V1
|
||||
|
||||
set_location_assignment PIN_C6 -to TX0_SW8_V2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V2
|
||||
|
||||
set_location_assignment PIN_B4 -to TX0_SW8_V3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW8_V3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW8_V3
|
||||
|
||||
set_location_assignment PIN_A4 -to TX0_SW9_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_A
|
||||
|
||||
set_location_assignment PIN_A3 -to TX0_SW9_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX0_SW9_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX0_SW9_B
|
||||
|
||||
set_location_assignment PIN_C14 -to TX1_DSA1[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[2]
|
||||
|
||||
set_location_assignment PIN_C15 -to TX1_DSA1[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[3]
|
||||
|
||||
set_location_assignment PIN_B17 -to TX1_DSA1[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[4]
|
||||
|
||||
set_location_assignment PIN_A17 -to TX1_DSA1[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[5]
|
||||
|
||||
set_location_assignment PIN_A16 -to TX1_DSA1[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA1[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA1[6]
|
||||
|
||||
set_location_assignment PIN_J6 -to TX1_DSA2[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[2]
|
||||
|
||||
set_location_assignment PIN_F10 -to TX1_DSA2[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[3]
|
||||
|
||||
set_location_assignment PIN_G10 -to TX1_DSA2[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[4]
|
||||
|
||||
set_location_assignment PIN_L10 -to TX1_DSA2[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[5]
|
||||
|
||||
set_location_assignment PIN_D9 -to TX1_DSA2[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_DSA2[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_DSA2[6]
|
||||
|
||||
set_location_assignment PIN_C9 -to TX1_LO1_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO1_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO1_MUXOUT
|
||||
|
||||
set_location_assignment PIN_B13 -to TX1_LO2_MUXOUT
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_LO2_MUXOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_LO2_MUXOUT
|
||||
|
||||
set_location_assignment PIN_B16 -to TX1_SW1_SW2_CTRL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW1_SW2_CTRL
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW1_SW2_CTRL
|
||||
|
||||
set_location_assignment PIN_G7 -to TX1_SW10_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_A
|
||||
|
||||
set_location_assignment PIN_D5 -to TX1_SW10_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW10_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW10_B
|
||||
|
||||
set_location_assignment PIN_D6 -to TX1_SW11_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_A
|
||||
|
||||
set_location_assignment PIN_E5 -to TX1_SW11_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW11_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW11_B
|
||||
|
||||
set_location_assignment PIN_A9 -to TX1_SW13_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW13_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW13_V1
|
||||
|
||||
set_location_assignment PIN_B8 -to TX1_SW14_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW14_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW14_V1
|
||||
|
||||
set_location_assignment PIN_E1 -to TX1_SW3_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_A
|
||||
|
||||
set_location_assignment PIN_D2 -to TX1_SW3_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW3_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW3_B
|
||||
|
||||
set_location_assignment PIN_J2 -to TX1_SW4_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_A
|
||||
|
||||
set_location_assignment PIN_K1 -to TX1_SW4_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW4_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW4_B
|
||||
|
||||
set_location_assignment PIN_L1 -to TX1_SW5_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_A
|
||||
|
||||
set_location_assignment PIN_K2 -to TX1_SW5_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW5_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW5_B
|
||||
|
||||
set_location_assignment PIN_H1 -to TX1_SW6_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_A
|
||||
|
||||
set_location_assignment PIN_F1 -to TX1_SW6_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW6_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW6_B
|
||||
|
||||
set_location_assignment PIN_B1 -to TX1_SW7_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_A
|
||||
|
||||
set_location_assignment PIN_C2 -to TX1_SW7_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW7_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW7_B
|
||||
|
||||
set_location_assignment PIN_B7 -to TX1_SW8_V1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V1
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V1
|
||||
|
||||
set_location_assignment PIN_C7 -to TX1_SW8_V2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V2
|
||||
|
||||
set_location_assignment PIN_A6 -to TX1_SW8_V3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW8_V3
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW8_V3
|
||||
|
||||
set_location_assignment PIN_B3 -to TX1_SW9_A
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_A
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_A
|
||||
|
||||
set_location_assignment PIN_B5 -to TX1_SW9_B
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TX1_SW9_B
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to TX1_SW9_B
|
||||
|
||||
set_location_assignment PIN_N11 -to CH0_RX2_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX2_LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX2_LED
|
||||
|
||||
set_location_assignment PIN_T13 -to CH0_RX_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_RX_LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_RX_LED
|
||||
|
||||
set_location_assignment PIN_R13 -to CH0_TX_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH0_TX_LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH0_TX_LED
|
||||
|
||||
set_location_assignment PIN_A10 -to CH1_RX2_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX2_LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX2_LED
|
||||
|
||||
set_location_assignment PIN_H7 -to CH1_RX_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_RX_LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_RX_LED
|
||||
|
||||
set_location_assignment PIN_G6 -to CH1_TX_LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED
|
||||
|
||||
# The zbx_top_cpld.v has to stand first as it contains a define statement.
|
||||
set_global_assignment -name VERILOG_FILE ./zbx_top_cpld.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_decoder.v
|
||||
set_global_assignment -name SDC_FILE ../../../constraints/timing/shared_constants.sdc
|
||||
set_global_assignment -name SDC_FILE ../../../cpld/db_spi_shared_constants.sdc
|
||||
set_global_assignment -name SDC_FILE zbx_top_cpld.sdc
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer_impl.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/reset_sync.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/rfnoc/utils/ctrlport_splitter.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave_to_ctrlport_master.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/basic_regs.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/power_regs.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/switch_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/dsa_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/led_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_top.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_shift.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/lo_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./zbx_cpld_core.v
|
||||
set_global_assignment -name VERILOG_FILE ../../ctrlport_byte_deserializer.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../cpld/reconfig_engine.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_combiner.v
|
||||
set_global_assignment -name VERILOG_FILE register_endpoints/atr_controller.v
|
||||
set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../lib/control/ram_2port_impl.vh
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/control/ram_2port.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/control/handshake.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/control/pulse_synchronizer.v
|
||||
set_global_assignment -name VERILOG_FILE ./ctrlport_window.v
|
||||
|
||||
set_global_assignment -name QSYS_FILE ip/flash/on_chip_flash.qsys
|
||||
set_global_assignment -name QSYS_FILE ip/osc/osc.qsys
|
||||
set_global_assignment -name QSYS_FILE ../../../cpld/ip/clkctrl/clkctrl.qsys
|
||||
set_global_assignment -name SOURCE_FILE db/zbx_top_cpld.cmp.rdb
|
||||
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx1_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx0_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx_dsa_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx1_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx0_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx_dsa_defaults.hex
|
||||
|
||||
set_global_assignment -name ENABLE_OCT_DONE OFF
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE WITH ERAM"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
|
||||
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY zbx_top_cpld
|
||||
|
||||
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -0,0 +1,374 @@
|
||||
#
|
||||
# Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
# Description:
|
||||
# Timing constraints for the ZBX daughterboard CPLD.
|
||||
#
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
#####################################################################
|
||||
# Main Clocks
|
||||
#####################################################################
|
||||
|
||||
## Input clocks.
|
||||
# Reliable clock: 50.0 MHz
|
||||
set reliable_clock_period 20.000
|
||||
create_clock -name ctrlport_clk -period $reliable_clock_period [get_ports CTRL_REG_CLK]
|
||||
|
||||
# PLL reference clock: 64 MHz (maximum)
|
||||
# Rounded down from 15.625 as this number divided by 2 has 4 decimal digits
|
||||
# which produces a warning.
|
||||
set prc_clock_period 15.62
|
||||
create_clock -name pll_ref_clk -period $prc_clock_period [get_ports CPLD_REFCLK]
|
||||
|
||||
# Create clock for the ControlPort SPI interface.
|
||||
# SPI clock is divided further down but only 3 clock cycles for processing are
|
||||
# available for this SPI slave
|
||||
set ctrl_sclk_period [expr {3 * $prc_clock_period}]
|
||||
create_clock -name mb_ctrl_sck -period $ctrl_sclk_period [get_ports MB_CTRL_SCK]
|
||||
|
||||
# Oscillator clock regenerated as the IP constraint for the "int_osc_clk" is not
|
||||
# yet available when processing this file.
|
||||
create_generated_clock -name osc_clk \
|
||||
-source [get_pins -compatibility_mode {*oscillator_dut|clkout}] \
|
||||
[get_pins {int_osc_clk_ctrl_i|altclkctrl_0|clkctrl_altclkctrl_0_sub_component|clkctrl1|outclk}]
|
||||
|
||||
# required to get rid of Warning (332056): PLL cross checking found inconsistent
|
||||
# PLL clock settings
|
||||
derive_pll_clocks
|
||||
|
||||
#####################################################################
|
||||
# Synthesizer sync interfaces
|
||||
#####################################################################
|
||||
# From MB FPGA
|
||||
#
|
||||
# ADClk_min and ADClk_max come from the ADCLK944 datasheet.
|
||||
# The CPLD receives it's clock from ADCLK944 U40. U40 also supplies a
|
||||
# clock to ADCLK944 U67, which drives clocks to the LO's. Therefore,
|
||||
# the clock arrives at the LO slightly later than it arrives at the
|
||||
# CPLD.
|
||||
#
|
||||
# The clock input to the CPLD is delayed by one ADCLK944 (U40) compared
|
||||
# to the input clock to the FPGA.
|
||||
#
|
||||
# ADClk_skew is also from the ADCLK944 datasheet,and is the maximum
|
||||
# difference between outputs in a single ADCLK944, and represents the
|
||||
# difference in arrival times of the clock at the
|
||||
# CPLD input and the input to U67.
|
||||
set ADClk_skew 0.015
|
||||
set ADClk_min 0.070
|
||||
set ADClk_max 0.130
|
||||
|
||||
# The longest SYNTH_SYNC trace going into a DB corresponds to DBO
|
||||
# Longest trace | Trace length | Trace delay
|
||||
# (multiple paths)| 7.909 in | 1.36 ns
|
||||
# MB_SYNTH_SYNC, DB0_SYNTH_SYNC_fs, DB0_SYNTH_SYNC
|
||||
# - for maximum propagation delay, this number will be rounded up
|
||||
set synth_board_delay 1.4
|
||||
# - for minimum propagation delay, we will consider a time of 0.
|
||||
|
||||
# Constrain the sync inputs to the CPLD driven from the MB FPGA.
|
||||
# synth_sync min/max output delays are defined in
|
||||
# fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
|
||||
|
||||
# Assume worst case as data being generated late and receiving an early clock:
|
||||
# - Max FPGA TCO
|
||||
# - Max FPGA clock propagation delay and minimum CPLD clock propagation delay
|
||||
# - Max data propagation delay
|
||||
# - Minimum delay on MC100EPT23 clock buffer
|
||||
set_input_delay -clock [get_clocks pll_ref_clk] \
|
||||
-max [expr {$prc_clock_period - $synth_sync_setup_requirement \
|
||||
+ $fpga_prc_clock_prop_max - $db_cpld_prc_clock_prop_min \
|
||||
+ $synth_board_delay \
|
||||
- $clock_translate_min }] \
|
||||
[get_ports MB_SYNTH_SYNC]
|
||||
|
||||
# Assume worst case as data being generated early and receiving an late clock:
|
||||
# - Min FPGA TCO
|
||||
# - Min data propagation delay (0)
|
||||
# - Min FPGA clock propagation delay and maximum CPLD clock propagation delay
|
||||
# - Maximum delay on MC100EPT23 clock buffer
|
||||
set_input_delay -clock [get_clocks pll_ref_clk] \
|
||||
-min [expr {$synth_sync_hold_requirement \
|
||||
- 0 \
|
||||
- $fpga_prc_clock_prop_min + $db_cpld_prc_clock_prop_max \
|
||||
+ $clock_translate_max}] \
|
||||
[get_ports MB_SYNTH_SYNC]
|
||||
|
||||
set rx_sync_ports {RX0_LO1_SYNC RX0_LO2_SYNC RX1_LO1_SYNC RX1_LO2_SYNC}
|
||||
set tx_sync_ports {TX0_LO1_SYNC TX0_LO2_SYNC TX1_LO1_SYNC TX1_LO2_SYNC}
|
||||
set sync_ports [get_ports [concat $rx_sync_ports $tx_sync_ports]]
|
||||
|
||||
# lo_setup and lo_hold are the constraints from the lmx2572 datasheet
|
||||
# for the LO's SYNC input.
|
||||
set lo_setup 2.5
|
||||
set lo_hold -2.0
|
||||
# The delay through an extra ADCLk944 reduces the maximum output delay,
|
||||
# but the skew of the root ADCLK944 (U40) might work against you, so the
|
||||
# skew increases the output delay.
|
||||
set_output_delay -clock [get_clocks pll_ref_clk]\
|
||||
-max [expr {$lo_setup - $ADClk_min + $ADClk_skew}] \
|
||||
$sync_ports
|
||||
|
||||
# The LO's hold requirement is modeled as a negative output delay. The
|
||||
# extra ADClk delay and the ADCLK skew can both work against you, so
|
||||
# they are both added to increase the minimum output delay.
|
||||
set_output_delay -clock [get_clocks pll_ref_clk]\
|
||||
-min [expr {-$lo_hold + $ADClk_max + $ADClk_skew}] \
|
||||
$sync_ports
|
||||
|
||||
#####################################################################
|
||||
# Timing exceptions
|
||||
#####################################################################
|
||||
## synchronizers
|
||||
set_false_path -to [get_registers *synchronizer_false_path\|value\[0\]\[*\]]
|
||||
|
||||
## PS SPI slave
|
||||
# sclk data to ctrlport_clk
|
||||
set_false_path -from [get_registers *spi_slave_async\|received_word\[*\]] \
|
||||
-to [get_registers *spi_slave_async\|data_out\[*\]]
|
||||
|
||||
# PLL driven data to sclk
|
||||
set_false_path -from [get_registers *spi_slave_async\|transmit_word\[*\]] \
|
||||
-to [get_registers *spi_slave_async\|transmit_bits\[*\]]
|
||||
|
||||
#####################################################################
|
||||
# MB CPLD <-> DP CPLD CTRL SPI interface
|
||||
#####################################################################
|
||||
# The timing constants of the MB CPLD are defined in
|
||||
# fpga/usrp3/top/x400/cpld/db_spi_shared_constants.sdc
|
||||
|
||||
# The longest trace on the PL SPI interface is (assuming 170.0 ps/in)
|
||||
# Longest trace | Trace length | Trace delay
|
||||
# DB0_SCK | 6.669 in | 1.134 ns
|
||||
set ctrl_spi_board_delay 1.134
|
||||
|
||||
# MB an dB CPLD both use PLL reference clock from a common clock chip.
|
||||
# The traces from that clock chip to the ICs are not length match
|
||||
# Assume a worst case clock difference of 2.5 ns at the IC inputs.
|
||||
# There is no direction defined. The clock can arrive faster or slower
|
||||
# on one IC.
|
||||
set ctrl_clock_diff 2.500
|
||||
|
||||
set ctrl_slave_inputs [get_ports {MB_CTRL_MOSI MB_CTRL_CS}]
|
||||
# calculate output delays back from capturing edge, add board delay and clock difference
|
||||
set_input_delay -clock mb_ctrl_sck -clock_fall \
|
||||
-max [expr {$prc_clock_period - $db_cpld_spi_max_out - $ctrl_spi_board_delay - $ctrl_clock_diff}] \
|
||||
$ctrl_slave_inputs
|
||||
# Assuming data is going without any delay, clock is arriving early at CPLD.
|
||||
# Negate minimum output delay as it is defined from the change to the start clock edge.
|
||||
set_input_delay -clock mb_ctrl_sck -clock_fall \
|
||||
-min [expr {- $db_cpld_spi_min_out - $ctrl_clock_diff}] \
|
||||
$ctrl_slave_inputs
|
||||
|
||||
set ctrl_slave_outputs [get_ports {MB_CTRL_MISO}]
|
||||
# Calculate remaining time of clock period based on MB CPLD maximum input delay.
|
||||
# Add board delay and clock difference.
|
||||
set_output_delay -clock mb_ctrl_sck \
|
||||
-max [expr {$prc_clock_period - $db_cpld_spi_max_in + $ctrl_spi_board_delay + $ctrl_clock_diff}] \
|
||||
$ctrl_slave_outputs
|
||||
# Assume no board delay just clock difference with rising edge occurring early at
|
||||
# DB CPLD and MB CPLD input constraint
|
||||
set_output_delay -clock mb_ctrl_sck \
|
||||
-min [expr {- $db_cpld_spi_min_in - $ctrl_clock_diff}] \
|
||||
$ctrl_slave_outputs
|
||||
|
||||
#####################################################################
|
||||
# LO SPI interface
|
||||
#####################################################################
|
||||
set lo_spi_clks [get_ports *X*_LO*_SCK]
|
||||
set lo_spi_output_ports [get_ports {*X*_LO*_SDI *X*_LO*_CSB}]
|
||||
set lo_spi_input_ports [get_ports {*X*_LO*_MUXOUT}]
|
||||
|
||||
# Use the worst-case board propagation delay.
|
||||
# Assuming 170.0 ps/in.
|
||||
# Longest trace | Trace length | Trace delay
|
||||
# RX0_LO1_SDI | 8.333 in | 1.416 ns
|
||||
# --------------------------------------------
|
||||
# Since lines are not managed individually, and since we should
|
||||
# have plenty of slack in this interface, we will conservatively use
|
||||
# twice the propagation time of the longest trace for all our
|
||||
# max delay calculations.
|
||||
set lo_spi_max_sclk_delay 3.000
|
||||
set lo_spi_min_sclk_delay 0.000
|
||||
set lo_spi_max_signal_delay 3.000
|
||||
set lo_spi_min_signal_delay 0.000
|
||||
|
||||
set lo_spi_min_tco 0.000
|
||||
set lo_spi_max_tco 10.000
|
||||
|
||||
set lo_spi_setup 10.000
|
||||
set lo_spi_hold 10.000
|
||||
|
||||
set lo_spi_clk_div 4
|
||||
|
||||
set lo_spi_clk_register [get_registers {zbx_cpld_core:zbx_cpld_core_i|lo_control:lo_control_i|spi_top:spi_top_i|spi_clgen:clgen|clk_out}]
|
||||
create_generated_clock -source [get_ports {CPLD_REFCLK}] \
|
||||
-name lo_spi_clk $lo_spi_clk_register \
|
||||
-divide_by $lo_spi_clk_div
|
||||
|
||||
create_generated_clock \
|
||||
-source $lo_spi_clk_register \
|
||||
-name lo_spi_clk_out $lo_spi_clks
|
||||
|
||||
# ----------------------------------------
|
||||
# -- Constraint for SPI CS and SDI --
|
||||
# ----------------------------------------
|
||||
|
||||
set_output_delay -clock lo_spi_clk_out \
|
||||
-max [expr {$lo_spi_setup + $lo_spi_max_signal_delay - $lo_spi_min_sclk_delay}] \
|
||||
$lo_spi_output_ports
|
||||
set_output_delay -clock lo_spi_clk_out \
|
||||
-min [expr {0 - $lo_spi_max_sclk_delay - $lo_spi_hold + $lo_spi_min_signal_delay }] \
|
||||
$lo_spi_output_ports
|
||||
|
||||
# -- Multi-cycle path for SPI CS and SDI --
|
||||
# ----------------------------------------
|
||||
# Both the CSB and SDI timing are defined in reference to the rising edge of SCLK, so we can merge the analysis.
|
||||
#
|
||||
# edge # 1 2 3 4 5
|
||||
# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/--
|
||||
# sclk __/-----------------------\_______________________/--------------
|
||||
# | launch edge (due to negedge reg)
|
||||
# | | |
|
||||
# 0 1 2 -- Edge used for setup analysis N = 2
|
||||
#
|
||||
# | | | |
|
||||
# 3 2 1 0 --(Setup -1) edge, in case of no hold multi-cycle path
|
||||
# |
|
||||
# \____ Edge used for hold = 3
|
||||
#
|
||||
# Analyzing this diagram, we can see that the setup edge of interest is located a sclk cycle
|
||||
# after the launch edge($lo_spi_clk_div) and that the hold margin has setup-1 edges after the launch edge,
|
||||
# or: lo_spi_clk_div - 1.
|
||||
set_multicycle_path -setup -start -to $lo_spi_output_ports [expr ($lo_spi_clk_div/2)]
|
||||
set_multicycle_path -hold -start -to $lo_spi_output_ports [expr ($lo_spi_clk_div-1)]
|
||||
|
||||
|
||||
# ----------------------------------------
|
||||
# -- Constraint for SPI MUXOUT --
|
||||
# ----------------------------------------
|
||||
|
||||
set_input_delay -clock lo_spi_clk_out -clock_fall \
|
||||
-max [expr {$lo_spi_max_sclk_delay + $lo_spi_max_tco + $lo_spi_max_signal_delay}] \
|
||||
$lo_spi_input_ports
|
||||
|
||||
set_input_delay -clock lo_spi_clk_out -clock_fall \
|
||||
-min [expr {$lo_spi_min_sclk_delay + $lo_spi_min_tco + $lo_spi_min_signal_delay}] \
|
||||
$lo_spi_input_ports
|
||||
|
||||
# -- Multi-cycle path for SPI MUXOUT --
|
||||
# ----------------------------------------
|
||||
# edge # 1 2 3 4 5 6 7 8
|
||||
# clk50 __/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/-----\_____/--
|
||||
# sclk __/-----------------------\_______________________/-----------------------\_______________________/--
|
||||
# muxout MSB | MSB-1
|
||||
# launch edge |
|
||||
# | | |
|
||||
# 0 1 2
|
||||
# \_ Edge used for setup analysis N = 2
|
||||
# | | | |
|
||||
# 3 2 1 0 - N-1 edge(if no hold is given)
|
||||
# |
|
||||
# \____ Edge used for hold = 3
|
||||
#
|
||||
# Analyzing this diagram, we can see that the setup edge of interest is located half a sclk cycle
|
||||
# after the launch edge($lo_spi_clk_div/2) and that the hold margin has ($lo_spi_clk_div/2)
|
||||
# of margin before the launch edge and setup-1 edges after the launch edge, to simplify:
|
||||
# ($lo_spi_clk_div/2+$lo_spi_clk_div/2-1) = lo_spi_clk_div - 1.
|
||||
set_multicycle_path -setup -end -from $lo_spi_input_ports [expr ($lo_spi_clk_div/2)]
|
||||
set_multicycle_path -hold -end -from $lo_spi_input_ports [expr ($lo_spi_clk_div-1)]
|
||||
|
||||
#####################################################################
|
||||
# Asynchronous IO
|
||||
#####################################################################
|
||||
# For general I/O that don't have tight timing constraints, we can constrain
|
||||
# these paths by creating a generic flip-flop that will interface to the
|
||||
# device.
|
||||
# For asynchronous outputs
|
||||
set generic_ext_flop_tsu 1
|
||||
set generic_ext_flop_th 0
|
||||
|
||||
# For asynchronous inputs
|
||||
set generic_ext_flop_max_tco 2
|
||||
set generic_ext_flop_min_tco 0
|
||||
|
||||
set async_outputs_prc {CH*_*X*_LED \
|
||||
RX*_DSA*_*[*] \
|
||||
TX*_DSA*[*] \
|
||||
*X*_SW*}
|
||||
set_output_delay -clock pll_ref_clk -max [expr $generic_ext_flop_tsu] \
|
||||
[get_ports $async_outputs_prc]
|
||||
set_output_delay -clock pll_ref_clk -min [expr 0 - $generic_ext_flop_th] \
|
||||
[get_ports $async_outputs_prc]
|
||||
|
||||
set_output_delay -clock osc_clk -max [expr $generic_ext_flop_tsu] \
|
||||
[get_ports {P*_ENABLE*}]
|
||||
set_output_delay -clock osc_clk -min [expr 0 - $generic_ext_flop_th] \
|
||||
[get_ports {P*_ENABLE*}]
|
||||
|
||||
set async_inputs {CTRL_REG_ARST}
|
||||
set_input_delay -clock ctrlport_clk -max [expr $generic_ext_flop_max_tco] \
|
||||
[get_ports $async_inputs]
|
||||
set_input_delay -clock ctrlport_clk -min [expr $generic_ext_flop_min_tco] \
|
||||
[get_ports $async_inputs]
|
||||
|
||||
set_input_delay -clock osc_clk -max [expr $generic_ext_flop_max_tco] \
|
||||
[get_ports {P7V_PG_*}]
|
||||
set_input_delay -clock osc_clk -min [expr $generic_ext_flop_min_tco] \
|
||||
[get_ports {P7V_PG_*}]
|
||||
|
||||
#####################################################################
|
||||
# MB FPGA GPIO
|
||||
#####################################################################
|
||||
# Some timing constants in this section are declared in
|
||||
# fpga/usrp3/top/x400/constraints/timing/shared_constants.sdc
|
||||
|
||||
set db_gpio_inputs [get_ports {MB_FPGA_GPIO[*]}]
|
||||
# Assume worst case as data being generated late and receiving an early clock:
|
||||
# - Max FPGA TCO
|
||||
# - Max data propagation delay
|
||||
# - Max FPGA clock propagation delay and minimum CPLD clock propagation delay
|
||||
# - Minimum delay on MC100EPT23 clock buffer
|
||||
set_input_delay -clock pll_ref_clk -clock_fall \
|
||||
-max [expr { $prc_clock_period/2 - $db_gpio_fpga_max_out \
|
||||
+ $db_gpio_board_max_delay \
|
||||
+ $fpga_prc_clock_prop_max - $db_cpld_prc_clock_prop_min \
|
||||
- $clock_translate_min}] \
|
||||
$db_gpio_inputs
|
||||
# Assume worst case as data being generated early and receiving an late clock:
|
||||
# - Min FPGA TCO
|
||||
# - Min data propagation delay (0)
|
||||
# - Min FPGA clock propagation delay and maximum CPLD clock propagation delay
|
||||
# - Maximum delay on MC100EPT23 clock buffer
|
||||
set_input_delay -clock pll_ref_clk -clock_fall \
|
||||
-min [expr {- $db_gpio_fpga_min_out \
|
||||
- $db_gpio_board_min_delay \
|
||||
- $fpga_prc_clock_prop_min + $db_cpld_prc_clock_prop_max \
|
||||
+ $clock_translate_max}] \
|
||||
$db_gpio_inputs
|
||||
|
||||
# output delay
|
||||
# maximum integer delays with slack of around 1ns
|
||||
set_output_delay -clock pll_ref_clk -max $db_gpio_cpld_max_out $db_gpio_inputs
|
||||
set_output_delay -clock pll_ref_clk -min $db_gpio_cpld_min_out $db_gpio_inputs
|
||||
|
||||
#####################################################################
|
||||
# Known Issue of On-Chip Flash
|
||||
#####################################################################
|
||||
# see https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2016/warning--332060---node---alteraonchipflash-onchipflash-alteraonc.html
|
||||
create_generated_clock -name flash_se_neg_reg \
|
||||
-source [get_pins { on_chip_flash:flash_i|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] \
|
||||
-divide_by 2 [get_pins { on_chip_flash:flash_i|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ]
|
||||
|
||||
#####################################################################
|
||||
# Clock uncertainty
|
||||
#####################################################################
|
||||
# Assign some uncertainty to all clocks
|
||||
set clock_uncertainty 0.150
|
||||
set_clock_uncertainty -to [get_clocks *] $clock_uncertainty
|
||||
derive_clock_uncertainty
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user