Files
b210-k7-fpga/top/x400/dboards/zbx/cpld/register_endpoints/README.md
T
a1d7c252c2 fpga: x400: zbx: Add support for ZBX CPLD
Co-authored-by: Cherwa Vang <cherwa.vang@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>


Original-commit: 99b841c75aa91709090cbf4046bf51b7ffb4f612
2021-06-10 11:56:58 -05:00

380 B

CPLD Default values

The memory of the CPLD is configured to set all the RF components to safe values. That means:

  • LEDs off
  • DSAs are set to maximum attenuation

The Python script memory_init_files/gen_defaults.py creates the .hex files that get read into the CPLD bitfile. This is run as part of the Makefile process, and the script does not have to be executed manually.