The top is defined in HDL source file zbx_top_cpld.v.
++ + Target Regmap = GPIO_REGMAP + +
+ ++ This port is defined in HDL source file zbx_top_cpld.v. +
+ ++ + Target Regmap = SPI_REGMAP + +
+ ++ This port is defined in HDL source file zbx_top_cpld.v. +
+ +| Value | +Name | + +
| 0 | + +
+
+
+ Uses the respective value of SW_CONFIG_REG as configuration. + + |
+
+
| 1 | + +
+
+
+ This option assumes the FPGA state to be assigned with: Bit 0 = RF 0 + RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3 + = RF 1 TX running. The configuration for each RF chain is built + up of the 2 bits for the RF chain (4 possible states: IDLE, RX only, + TX only, TX/RX). + + |
+
+
| 2 | + +
+
+
+ The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states. + + |
+
+
+ This enumerated type is defined in HDL source file atr_controller.v. +
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file atr_controller.v.
+ +| Bits | Name |
| 31..24 | +
+
+ Current active configuration for DSAs of RF 1. + + |
+
| 23..16 | +
+
+ Current active configuration for DSAs of RF 0. + + |
+
| 15..8 | +
+
+ Current active configuration for switches and LEDs of RF 1. + + |
+
| 7..0 | +
+
+ Current active configuration for switches and LEDs of RF 0. + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file atr_controller.v.
+ +| Bits | Name | ||||||||
| 31..26 | +
+ Reserved + + + |
+ ||||||||
| 25..24 | +
+ RF1_DSA_OPTION (initialvalue=SW_DEFINED) +Option used for DSAs of RF 1. + ++ The values for this bitfield are in the ATR_OPTIONS table. + (show here) + +
+
+
+
+
+
+ Contains the options available for RF 0 and RF 1. The chosen setting
+ affects how the active configuration of up to 8 bits is derived.
+
+
+
+ This enumerated type is defined in HDL source file atr_controller.v. + + + |
+ ||||||||
| 23..18 | +
+ Reserved + + + |
+ ||||||||
| 17..16 | +
+ RF0_DSA_OPTION (initialvalue=SW_DEFINED) +Option used for DSAs of RF 0. + ++ The values for this bitfield are in the ATR_OPTIONS table. + (show here) + +
+
+
+
+
+
+ Contains the options available for RF 0 and RF 1. The chosen setting
+ affects how the active configuration of up to 8 bits is derived.
+
+
+
+ This enumerated type is defined in HDL source file atr_controller.v. + + + |
+ ||||||||
| 15..10 | +
+ Reserved + + + |
+ ||||||||
| 9..8 | +
+ RF1_OPTION (initialvalue=SW_DEFINED) +Option used for switches and LEDs of RF 1. + ++ The values for this bitfield are in the ATR_OPTIONS table. + (show here) + +
+
+
+
+
+
+ Contains the options available for RF 0 and RF 1. The chosen setting
+ affects how the active configuration of up to 8 bits is derived.
+
+
+
+ This enumerated type is defined in HDL source file atr_controller.v. + + + |
+ ||||||||
| 7..2 | +
+ Reserved + + + |
+ ||||||||
| 1..0 | +
+ RF0_OPTION (initialvalue=SW_DEFINED) +Option used for switches and LEDs of RF 0. + ++ The values for this bitfield are in the ATR_OPTIONS table. + (show here) + +
+
+
+
+
+
+ Contains the options available for RF 0 and RF 1. The chosen setting
+ affects how the active configuration of up to 8 bits is derived.
+
+
+
+ This enumerated type is defined in HDL source file atr_controller.v. + + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file atr_controller.v.
+ +| Value | +Name | + +|
| Dec | + +Hex | + +|
| 16386 | + +0x00004002 | + ++ + + | + +
| 537986577 | + +0x20110611 | + ++ + + | + +
| 553848841 | + +0x21031009 | + ++ + + | + +
+ This enumerated type is defined in HDL source file basic_regs.v. +
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file basic_regs.v.
+ +| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..0 | +
+
+ Board ID corresponds to the las 16 digits of the daughterboard part number. + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file basic_regs.v.
+ +| Bits | Name |
| 31..0 | +
+
+ Returns the revision in YYMMDDHH format + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file basic_regs.v.
+ +| Bits | Name |
| 31..0 | +
+
+ Returns the oldest compatible revision in YYMMDDHH format + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file basic_regs.v.
+ +| Bits | Name |
| 31..0 | +
+
+ Returns the value written here previously. + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file basic_regs.v.
+ +| Bits | Name |
| 31..28 | +
+
+ 0x0 in case the git status was clean |
+
| 27..0 | +
+
+ 7 hex digit hash code of the commit + + |
+
Target regmap = ATR_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = LO_CONTROL_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = LED_SETUP_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = SWITCH_SETUP_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = DSA_SETUP_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +The following registers control the digital step attenuators (DSA).
+There are two ways to set the DSA values, which are applied to the DB ICs.
+The ...DSA_ATR registers can be used to access the raw +values of each ATR configuration.
+Gain tables can be used as intermediate step to abstract from the +raw DB values. This gain table can be modified using the ...DSA_TABLE +registers according to the content of the registers from the first +option. Initially each gain table is empty (all zeros). Each gain +table entry can be accessed at any time. Once the table is filled with +values the ...DSA_TABLE_SELECT registers can be used to get one gain +table entry with index TABLE_INDEX and write it to the appropriate ATR +configuration given by the address (see show extended info link below +the register array headlines)
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00001F1F |
This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Tx0 DSAs by accessing the raw attenuation levels.
+This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..13 | +
+ Reserved + + + |
+
| 12..8 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..5 | +
+ Reserved + + + |
+
| 4..0 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00001F1F |
This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Tx1 DSAs by accessing the raw attenuation levels.
+This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..13 | +
+ Reserved + + + |
+
| 12..8 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..5 | +
+ Reserved + + + |
+
| 4..0 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x0000FFFF |
This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Rx0 DSAs by accessing the raw attenuation levels.
+This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..12 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/} |
+
| 11..8 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..4 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 3..0 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x0000FFFF |
This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Rx1 DSAs by accessing the raw attenuation levels.
+This register array can hold settings for all ATR configurations. +The register index equals the ATR configuration. +The active configuration can be selected in ATR_REGMAP. +Independently all configurations can be read/written at any time.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..12 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/} |
+
| 11..8 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..4 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 3..0 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Tx0 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..8 | +
+ Reserved + + + |
+
| 7..0w | +
+
+
+
+
+ Gain table index to be used for getting the raw attenuation values. |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Tx1 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..8 | +
+ Reserved + + + |
+
| 7..0w | +
+
+
+
+
+ Gain table index to be used for getting the raw attenuation values. |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Rx0 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..8 | +
+ Reserved + + + |
+
| 7..0w | +
+
+
+
+
+ Gain table index to be used for getting the raw attenuation values. |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file dsa_control.v.
+It uses RegType DSA_TABLE_CONTROL which is defined in HDL source file dsa_control.v.
Controls the Rx1 DSAs by using the gain table to translate the table +index to raw attenuation levels. The register offset (i) is targeting +an ATR configuration to store the values from the gain table.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..8 | +
+ Reserved + + + |
+
| 7..0w | +
+
+
+
+
+ Gain table index to be used for getting the raw attenuation values. |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00001F1F |
This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Provides access to the gain table for Tx0.
+Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in TX0_DSA_TABLE_SELECT to +modify the ATR configurations.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..13 | +
+ Reserved + + + |
+
| 12..8 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..5 | +
+ Reserved + + + |
+
| 4..0 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00001F1F |
This register is defined in HDL source file dsa_control.v.
+It uses RegType TX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Provides access to the gain table for Tx1.
+Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in TX1_DSA_TABLE_SELECT to +modify the ATR configurations.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..13 | +
+ Reserved + + + |
+
| 12..8 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..5 | +
+ Reserved + + + |
+
| 4..0 | +
+
+
+
+
+ Sets the attenuation level for Tx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 31 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x0000FFFF |
This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Provides access to the gain table for Rx0.
+Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in RX0_DSA_TABLE_SELECT to +modify the ATR configurations.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..12 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/} |
+
| 11..8 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..4 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 3..0 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x0000FFFF |
This register is defined in HDL source file dsa_control.v.
+It uses RegType RX_DSA_CONTROL which is defined in HDL source file dsa_control.v.
Provides access to the gain table for Rx1.
+Each entry i will be saved in the gain table without any implications +on HW. Enables SW to use the table index in RX1_DSA_TABLE_SELECT to +modify the ATR configurations.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..12 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3b(to input of IF1 Amplifier 2). The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges).. {BR/} |
+
| 11..8 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA 3a and 3b. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 7..4 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA2. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
| 3..0 | +
+
+
+
+
+ Sets the attenuation level for Rx DSA1. The resolution attenuation is 1 dB, with an attenuation range from 1 to 15 dB. Write this field with the +attenuation setting desired. Writing zero to this field results in no attenuation (different insertion loss expected for different frequency ranges). |
+
Target regmap = BASIC_REGS_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = DB_CONTROL_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00000000 |
This register is defined in HDL source file led_control.v.
+It uses RegType LED_CONTROL_TYPE which is defined in HDL source file led_control.v.
| Value | +Name | + +
| 0 | + ++ + + | + +
| 1 | + ++ + + | + +
| 2 | + ++ + + | + +
| 3 | + ++ + + | + +
| 4 | + ++ + + | + +
| 5 | + ++ + + | + +
| 6 | + ++ + + | + +
| 7 | + ++ + + | + +
+ This enumerated type is defined in HDL source file lo_control.v. +
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file lo_control.v.
+ +| Bits | Name | ||||||||||||||||||
| 31..29 | +
+ Reserved + + + |
+ ||||||||||||||||||
| 28w | +
+ LO_SPI_START_TRANSACTION (Strobe, initialvalue=0) +Strobe this bit high to start the SPI transaction with the bitfields below + + |
+ ||||||||||||||||||
| 27 | +
+ Reserved + + + |
+ ||||||||||||||||||
| 26..24w | +
+ LO_SELECT (Strobe, initialvalue=TX0_LO1) +Sets the CS to the selected LO. The CS will assert until after LO_SPI_START_TRANSACTION has been asserted. + ++ The values for this bitfield are in the LO_CHIP_SELECT table. + (show here) + +
+
+
+
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file lo_control.v. + + + |
+ ||||||||||||||||||
| 23w | +
+
+ Set this bit to '1' to read from the LMX2572. Set this bit to '0' to write to the LMX2572. + + |
+ ||||||||||||||||||
| 22..16w | +
+ LO_SPI_WT_ADDR (initialvalue=0) +7 bit address of the LMX2572 + + |
+ ||||||||||||||||||
| 15..0w | +
+ LO_SPI_WT_DATA (initialvalue=0) +Write Data to the LMX2572 + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file lo_control.v.
+ +| Bits | Name | ||||||||||||||||||
| 31 | +
+ LO_SPI_DATA_VALID (initialvalue=0) +Returns '1' when a read SPI transaction is complete. This bit will remain high until a new SPI transaction has started. + i.e. LO_SPI_START_TRANSACTION is strobed. Poll this when expecting data from a read transaction. + + |
+ ||||||||||||||||||
| 30 | +
+
+ If this bit returns '1' then LMX2572 is ready for transaction. If it returns '0' then it is busy with a previous SPI transaction. + Poll this bit before starting a SPI transaction. + + |
+ ||||||||||||||||||
| 29..27 | +
+ Reserved + + + |
+ ||||||||||||||||||
| 26..24 | +
+ LO_SELECT_STATUS (initialvalue=TX0_LO1) +Returns the current selected CS. This bitfield will return the value written to LO_SELECT bitfield in the LO_SPI_SETUP reg. + ++ The values for this bitfield are in the LO_CHIP_SELECT table. + (show here) + +
+
+
+
+
+
+
+
+
+
+ This enumerated type is defined in HDL source file lo_control.v. + + + |
+ ||||||||||||||||||
| 23 | +
+ Reserved + + + |
+ ||||||||||||||||||
| 22..16 | +
+ LO_SPI_RD_ADDR (initialvalue=0) +Returns the address of the current SPI address setup + + |
+ ||||||||||||||||||
| 15..0 | +
+ LO_SPI_RD_DATA (initialvalue=0) +Returns the data of the SPI read. This bitfield will return 0x0000 until LO_SPI_DATA_VALID is true. This bit field will maintain it's + read value until a new SPI transaction has started. i.e. LO_SPI_START_TRANSACTION is strobed. + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+|||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file lo_control.v.
+ +This regmap has readablestrobes="true", so all strobe bits are readable by +default. This attribute should only be used for older regmaps to maintain +compatibility with previous versions of XmlParse. New regmaps should either +use the 'clearable' attribute or should explicitly define readable bits +in the same bit position as the strobe bits.
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file power_regs.v.
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file power_regs.v.
+ +| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..8 | +
+ Reserved + + + |
+
| 7..2 | +
+ Reserved + + + |
+
| 1 | +
+
+ Returns status of 7V switching regulator B. |
+
| 0 | +
+
+ Returns status of 7V switching regulator A. |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value = 0x00000000 +
+ +This register is defined in HDL source file power_regs.v.
+ +Prepare the data... +
The Max 10 FPGA build should generate a *cfm0_auto.rpd + file The *.rpd file is a "raw programming + data" file holding all data related to the + configuration image (CFM0). There are two + important items to note regarding the addresses. + First the *rpd data uses byte addresses. + Second, the start/end addresses defined by + FLASH_PRIMARY_IMAGE_ADDR_ENUM are 32-bit word addresses
As a sanity check, verify the size of the raw + programming data for CFM0 correspond to the address + range of FLASH_PRIMARY_IMAGE_ADDR_ENUM. Do this by + reading the values from FLASH_CFM0_START_ADDR_REG and + FLASH_CFM0_END_ADDR, subtract both values, add one and + multiply by four. +
Having passed the sanity check the *.rpd data must + now be manipulated into the form required by Altera's + on-chip flash IP. Two operations must be performed. + First the data must be converted from bytes to 32-bit + words. Second the bit order must be reversed. This is + illustrated in in the following table which shows byte + address and data from the *.rpd file compared to the + word address and data to be written to the on-chip + flash. +
| .Map Addr | .Map Data | Flash Addr | Flash Data |
| 0x2B800 | 0x01 | 0xAC00 | 0x8040C020 |
| 0x2B801 | 0x02 | ||
| 0x2B802 | 0x03 | ||
| 0x2B803 | 0x04 | ||
| 0x2B804 | 0x05 | 0xAC01 | 0xA060E010 |
| 0x2B805 | 0x06 | ||
| 0x2B806 | 0x07 | ||
| 0x2B807 | 0x08 |
The resulting set of flash address data pairs should + be used when writing FLASH_ADDR_REG and + FLASH_WRITE_DATA_REG to update the CFM0 image. + However, prior to writing the new image the old image + must be erased. +
Erase the current primary flash image... +
Write the new primary flash image... +
Verify the new primary flash image... +
After the flash has been erased, programmed, and verified, a power + cycle is required for the new image to become active. +
+| Value | +Name | + +|
| Dec | + +Hex | + +|
| 4096 | + +0x01000 | + ++ + + | + +
| 39936 | + +0x09C00 | + ++ + + | + +
| 75775 | + +0x127FF | + ++ + + | + +
+ This enumerated type is defined in HDL source file reconfig_engine.v. +
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file reconfig_engine.v.
+ +| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..17 | +
+ Reserved + + + |
+
| 16 | +
+
+ This bit is asserted when the flash can hold an image with memory + initialization. + + |
+
| 15..14 | +
+ Reserved + + + |
+
| 13 | +
+
+ This bit is asserted when write operation fails. Clear this error + by strobing the CLEAR_FLASH_WRITE_ERROR_STB bit of this register. In + the event of a write error... + |
+
| 12 | +
+
+ This bit is de-asserted when a write operation is in progress. Poll + this bit after strobing the FLASH_WRITE_STB bit of + FLASH_CONTROL_REG to determine when the write operation has + completed, then check the FLASH_WRITE_ERR bit to verify the + operation was successful. + + |
+
| 11..10 | +
+ Reserved + + + |
+
| 9 | +
+
+ This bit is asserted when an erase operation fails. Clear this + error by strobing CLEAR_FLASH_ERASE_ERROR_STB of this register. In + the event of an erase error... + |
+
| 8 | +
+
+ This bit is de-asserted when an erase operation is in progress. Poll + this bit after strobing the FLASH_ERASE_STB bit of + FLASH_CONTROL_REG to determine when the erase operation has + completed, then check the FLASH_ERASE_ERR bit to verify the + operation was successful. + + |
+
| 7..6 | +
+ Reserved + + + |
+
| 5 | +
+
+ This bit is asserted when a read operation fails. Clear this error + by strobing the CLEAR_FLASH_READ_ERROR_STB of this register. In the + event of a read error... + |
+
| 4 | +
+
+ This bit is de-asserted when a read operation is in progress. Poll + this bit after strobing the FLASH_READ_STB bit of + FLASH_CONTROL_REG to determine when the read operation has + completed, then check the FLASH_READ_ERR bit to verify the + operation was successful. + + |
+
| 3..1 | +
+ Reserved + + + |
+
| 0 | +
+
+ This bit is asserted when the flash is write protected and + de-asserted when write protection is disabled. + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file reconfig_engine.v.
+ +| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..16 | +
+ Reserved + + + |
+
| 15..11 | +
+ Reserved + + + |
+
| 10w | +
+ CLEAR_FLASH_ERASE_ERROR_STB (Strobe) +Strobe this bit to clear an erase error. + + |
+
| 9w | +
+ CLEAR_FLASH_WRITE_ERROR_STB (Strobe) +Strobe this bit to clear a write error. + + |
+
| 8w | +
+ CLEAR_FLASH_READ_ERROR_STB (Strobe) +Strobe this bit to clear a read error. + + |
+
| 7..5w | +
+
+ Defines the sector to be erased. Has to be set latest with the
+ write access which starts the erase operation by strobing
+ FLASH_ERASE_STB. |
+
| 4w | +
+
+ Strobe this bit to erase the primary Max10 configuration image + (CFM0). + |
+
| 3w | +
+
+ Strobe this bit to write the data contained in + FLASH_WRITE_DATA_REG to the flash address identified in + FLASH_ADDR_REG. + |
+
| 2w | +
+
+ Strobe this bit to read data from the flash address identified in + FLASH_ADDR_REG. + |
+
| 1w | +
+
+ Strobe this bit to disable write protection to the section of the + Max 10 on-chip flash storing the primary configuration image + (CFM0). + |
+
| 0w | +
+
+ Strobe this bit to enable write protection to the section of the + Max 10 on-chip flash storing the primary configuration image + (CFM0). + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file reconfig_engine.v.
+ +| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23..17 | +
+ Reserved + + + |
+
| 16..0 | +
+
+ This field holds the target address for the next read or + write operation. Set this field prior to strobing the + FLASH_WRITE_STB and FLASH_READ_STB bits of + FLASH_CONTROL_REG. Valid addresses are defined by the + FLASH_PRIMARY_IMAGE_ADDR_ENUM enumeration. + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file reconfig_engine.v.
+ +| Bits | Name |
| 31..0w | +
+
+ Data in this register will be written to the flash at the address + identified in FLASH_ADDR_REG when a successful write operation + is executed. + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file reconfig_engine.v.
+ +| Bits | Name |
| 31..0 | +
+
+ This register contains data read from the flash address identified + in FLASH_ADDR_REG after a successful read operation is executed. + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file reconfig_engine.v.
+ +| Bits | Name |
| 31..0 | +
+
+ Start address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). + + |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Value not specified +
+ +This register is defined in HDL source file reconfig_engine.v.
+ +| Bits | Name |
| 31..0 | +
+
+ Last address of CFM0 image within flash memory (as defined in FLASH_PRIMARY_IMAGE_ADDR_ENUM). + + |
+
Target regmap = BASIC_REGS_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = RECONFIG_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = POWER_REGS_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +Target regmap = DB_CONTROL_REGMAP
+ (show extended info) +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
This window is defined in HDL source file zbx_top_cpld.v.
+ +
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00000000 |
This register is defined in HDL source file switch_control.v.
+It uses RegType TX_PATH_CONTROL which is defined in HDL source file switch_control.v.
| Bits | Name |
| 31..27 | +
+ Reserved + + + |
+
| 26 | +
+
+ Control for Tx Switch 13 LO path.
+ The configuration of this switch changes between TX paths. |
+
| 25 | +
+ Reserved + + + |
+
| 24 | +
+
+ Control for Tx0 Switch 13 LO path.
+ The configuration of this switch changes between TX paths. |
+
| 23..22 | +
+ Reserved + + + |
+
| 21..20 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 19..18 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 17..16 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 15 | +
+ Reserved + + + |
+
| 14..12 | +
+
+ Control for Tx Switch 8, note this is one hot encoding and not binary.
+ The configuration of this switch changes between TX paths. |
+
| 11..10 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 9..8 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 7..6 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 5..4 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 3..2 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 1 | +
+ Reserved + + + |
+
| 0 | +
+ TX_SWITCH_1_2 (initialvalue=0) +Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00000000 |
This register is defined in HDL source file switch_control.v.
+It uses RegType TX_PATH_CONTROL which is defined in HDL source file switch_control.v.
| Bits | Name |
| 31..27 | +
+ Reserved + + + |
+
| 26 | +
+
+ Control for Tx Switch 13 LO path.
+ The configuration of this switch changes between TX paths. |
+
| 25 | +
+ Reserved + + + |
+
| 24 | +
+
+ Control for Tx0 Switch 13 LO path.
+ The configuration of this switch changes between TX paths. |
+
| 23..22 | +
+ Reserved + + + |
+
| 21..20 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 19..18 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 17..16 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 15 | +
+ Reserved + + + |
+
| 14..12 | +
+
+ Control for Tx Switch 8, note this is one hot encoding and not binary.
+ The configuration of this switch changes between TX paths. |
+
| 11..10 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 9..8 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 7..6 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 5..4 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 3..2 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 1 | +
+ Reserved + + + |
+
| 0 | +
+ TX_SWITCH_1_2 (initialvalue=0) +Write 0 to select Tx IF2 filter 2, CF = 2050 MHz, BW = 400 MHz |
+
+
+
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+
+
+
+
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+
+
+
+
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+
+
+
+
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+
+
+
+
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+
+||||||||||
+
+
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+
+
+
+
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+
+
+
+
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+
+
Initial Values
+
| default | => | 0x00000000 |
This register is defined in HDL source file switch_control.v.
+It uses RegType RX_PATH_CONTROL which is defined in HDL source file switch_control.v.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23 | +
+ Reserved + + + |
+
| 22..20 | +
+
+ Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground. |
+
| 19 | +
+ Reserved + + + |
+
| 18 | +
+
+ Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths. |
+
| 17 | +
+ Reserved + + + |
+
| 16 | +
+
+ Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths. |
+
| 15 | +
+ Reserved + + + |
+
| 14 | +
+ RX_SWITCH_7_8 (initialvalue=0) +Shared control for Rx switch 7 and switch 8. |
+
| 13..12 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 11..10 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 9 | +
+ Reserved + + + |
+
| 8 | +
+
+ note to digital designer: control A is the only control, and control B is tied to ground |
+
| 7 | +
+ Reserved + + + |
+
| 6..4 | +
+
+ Control for Rx Switch 3, note this is one hot encoding and not binary.
+ The configuration of this switch changes between RX paths. |
+
| 3 | +
+ Reserved + + + |
+
| 2 | +
+
+ note to digital designer: control A is the only control, and control B is pulled high |
+
| 1..0 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+||||||||||
+
+
|
+
+
+
+
|
+
+
+
+
|
+
+
Initial Values
+
| default | => | 0x00000000 |
This register is defined in HDL source file switch_control.v.
+It uses RegType RX_PATH_CONTROL which is defined in HDL source file switch_control.v.
| Bits | Name |
| 31..24 | +
+ Reserved + + + |
+
| 23 | +
+ Reserved + + + |
+
| 22..20 | +
+
+ Control for Rx Switch 11, note to digital designer: Control V2 is pulled to ground. |
+
| 19 | +
+ Reserved + + + |
+
| 18 | +
+
+ Control for Rx Switch 10 LO path. The configuration of this switch changes between RX paths. |
+
| 17 | +
+ Reserved + + + |
+
| 16 | +
+
+ Control for Rx Switch 9 LO path. The configuration of this switch changes between RX paths. |
+
| 15 | +
+ Reserved + + + |
+
| 14 | +
+ RX_SWITCH_7_8 (initialvalue=0) +Shared control for Rx switch 7 and switch 8. |
+
| 13..12 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 11..10 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+
| 9 | +
+ Reserved + + + |
+
| 8 | +
+
+ note to digital designer: control A is the only control, and control B is tied to ground |
+
| 7 | +
+ Reserved + + + |
+
| 6..4 | +
+
+ Control for Rx Switch 3, note this is one hot encoding and not binary.
+ The configuration of this switch changes between RX paths. |
+
| 3 | +
+ Reserved + + + |
+
| 2 | +
+
+ note to digital designer: control A is the only control, and control B is pulled high |
+
| 1..0 | +
+
+ note to digital designer: control A is LSB, and control B is MSB |
+