a1d7c252c2
Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Original-commit: 99b841c75aa91709090cbf4046bf51b7ffb4f612
342 lines
12 KiB
Verilog
342 lines
12 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: atr_controller
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//
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// Description:
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// Controller of the ATR state configuration for the other register endpoints.
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//
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`default_nettype none
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module atr_controller #(
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parameter [19:0] BASE_ADDRESS = 0,
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parameter [19:0] SIZE_ADDRESS = 0
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) (
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// Clock and reset
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// ATR state of FPGA
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// Assumes the following assignment on the FPGA:
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// {tx_running[1], rx_running[1], tx_running[0], rx_running[0]}
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// where the array index indicates the RF chain.
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input wire [ 3:0] atr_fpga_state,
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// derived configuration
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output reg [ 7:0] atr_config_dsa_rf0 = 8'b0,
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output reg [ 7:0] atr_config_dsa_rf1 = 8'b0,
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output reg [ 7:0] atr_config_rf0 = 8'b0,
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output reg [ 7:0] atr_config_rf1 = 8'b0
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);
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`include "../regmap/atr_regmap_utils.vh"
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`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
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//----------------------------------------------------------
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// Internal registers
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//----------------------------------------------------------
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reg [ RF0_OPTION_SIZE-1:0] option_rf0 = SW_DEFINED;
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reg [ RF1_OPTION_SIZE-1:0] option_rf1 = SW_DEFINED;
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reg [RF0_DSA_OPTION_SIZE-1:0] option_dsa_rf0 = SW_DEFINED;
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reg [RF1_DSA_OPTION_SIZE-1:0] option_dsa_rf1 = SW_DEFINED;
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reg [ SW_RF0_CONFIG_SIZE-1:0] sw_atr_config_rf0 = {SW_RF0_CONFIG_SIZE {1'b0}};
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reg [ SW_RF1_CONFIG_SIZE-1:0] sw_atr_config_rf1 = {SW_RF1_CONFIG_SIZE {1'b0}};
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reg [SW_RF0_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf0 = {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
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reg [SW_RF1_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf1 = {SW_RF1_DSA_CONFIG_SIZE {1'b0}};
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//----------------------------------------------------------
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// Handling of CtrlPort
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//----------------------------------------------------------
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wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
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always @(posedge ctrlport_clk) begin
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// reset internal registers and responses
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if (ctrlport_rst) begin
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option_rf0 <= SW_DEFINED;
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option_rf1 <= SW_DEFINED;
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option_dsa_rf0 <= SW_DEFINED;
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option_dsa_rf1 <= SW_DEFINED;
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sw_atr_config_rf0 <= {SW_RF0_CONFIG_SIZE {1'b0}};
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sw_atr_config_rf1 <= {SW_RF1_CONFIG_SIZE {1'b0}};
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sw_atr_config_dsa_rf0 <= {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
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sw_atr_config_dsa_rf1 <= {SW_RF1_DSA_CONFIG_SIZE {1'b0}};
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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end else begin
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// write requests
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if (s_ctrlport_req_wr) begin
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// always issue an ack and no data
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= {32{1'bx}};
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + OPTION_REG: begin
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option_rf0 <= s_ctrlport_req_data[RF0_OPTION_MSB : RF0_OPTION];
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option_rf1 <= s_ctrlport_req_data[RF1_OPTION_MSB : RF1_OPTION];
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option_dsa_rf0 <= s_ctrlport_req_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION];
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option_dsa_rf1 <= s_ctrlport_req_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION];
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end
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BASE_ADDRESS + SW_CONFIG_REG: begin
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sw_atr_config_rf0 <= s_ctrlport_req_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG];
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sw_atr_config_rf1 <= s_ctrlport_req_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG];
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sw_atr_config_dsa_rf0 <= s_ctrlport_req_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG];
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sw_atr_config_dsa_rf1 <= s_ctrlport_req_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG];
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end
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// error on undefined address
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// read requests
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end else if (s_ctrlport_req_rd) begin
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// default assumption: valid request
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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s_ctrlport_resp_data <= {32{1'b0}};
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case (s_ctrlport_req_addr)
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BASE_ADDRESS + CURRENT_CONFIG_REG: begin
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s_ctrlport_resp_data[CURRENT_RF0_CONFIG_MSB : CURRENT_RF0_CONFIG] <= atr_config_rf0;
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s_ctrlport_resp_data[CURRENT_RF1_CONFIG_MSB : CURRENT_RF1_CONFIG] <= atr_config_rf1;
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s_ctrlport_resp_data[CURRENT_RF0_DSA_CONFIG_MSB : CURRENT_RF0_DSA_CONFIG] <= atr_config_dsa_rf0;
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s_ctrlport_resp_data[CURRENT_RF1_DSA_CONFIG_MSB : CURRENT_RF1_DSA_CONFIG] <= atr_config_dsa_rf1;
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end
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BASE_ADDRESS + OPTION_REG: begin
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s_ctrlport_resp_data[RF0_OPTION_MSB : RF0_OPTION] <= option_rf0;
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s_ctrlport_resp_data[RF1_OPTION_MSB : RF1_OPTION] <= option_rf1;
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s_ctrlport_resp_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION] <= option_dsa_rf0;
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s_ctrlport_resp_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION] <= option_dsa_rf1;
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end
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BASE_ADDRESS + SW_CONFIG_REG: begin
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s_ctrlport_resp_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG] <= sw_atr_config_rf0;
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s_ctrlport_resp_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG] <= sw_atr_config_rf1;
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s_ctrlport_resp_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG] <= sw_atr_config_dsa_rf0;
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s_ctrlport_resp_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG] <= sw_atr_config_dsa_rf1;
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end
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// error on undefined address
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default: begin
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s_ctrlport_resp_data <= {32{1'b0}};
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// no response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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// no request
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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//----------------------------------------------------------
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// derive configuration
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//----------------------------------------------------------
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always @(posedge ctrlport_clk) begin
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case (option_rf0)
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SW_DEFINED: begin
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atr_config_rf0 <= sw_atr_config_rf0;
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end
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CLASSIC_ATR: begin
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atr_config_rf0 <= {6'b0, atr_fpga_state[1:0]};
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end
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FPGA_STATE: begin
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atr_config_rf0 <= {4'b0, atr_fpga_state};
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end
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endcase
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case (option_rf1)
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SW_DEFINED: begin
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atr_config_rf1 <= sw_atr_config_rf1;
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end
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CLASSIC_ATR: begin
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atr_config_rf1 <= {6'b0, atr_fpga_state[3:2]};
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end
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FPGA_STATE: begin
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atr_config_rf1 <= {4'b0, atr_fpga_state};
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end
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endcase
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case (option_dsa_rf0)
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SW_DEFINED: begin
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atr_config_dsa_rf0 <= sw_atr_config_dsa_rf0;
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end
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CLASSIC_ATR: begin
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atr_config_dsa_rf0 <= {6'b0, atr_fpga_state[1:0]};
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end
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FPGA_STATE: begin
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atr_config_dsa_rf0 <= {4'b0, atr_fpga_state};
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end
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endcase
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case (option_dsa_rf1)
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SW_DEFINED: begin
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atr_config_dsa_rf1 <= sw_atr_config_dsa_rf1;
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end
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CLASSIC_ATR: begin
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atr_config_dsa_rf1 <= {6'b0, atr_fpga_state[3:2]};
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end
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FPGA_STATE: begin
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atr_config_dsa_rf1 <= {4'b0, atr_fpga_state};
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end
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endcase
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="ATR_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="ATR_REGISTERS">
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// <info>
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// This regmap contains settings for the active configuration of RF 0 and 1.
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// There are two sets of configurations. One set comprises RF switches and
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// LEDs, the other set comprises the attenuators (DSA).
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// </info>
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//
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// <enumeratedtype name="ATR_OPTIONS">
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// <info>
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// Contains the options available for RF 0 and RF 1. The chosen setting
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// affects how the active configuration of up to 8 bits is derived.
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// </info>
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// <value name="SW_DEFINED" integer="0">
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// <info>
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// Uses the respective value of @.SW_CONFIG_REG as configuration.
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// </info>
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// </value>
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// <value name="CLASSIC_ATR" integer="1">
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// <info>
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// This option assumes the FPGA state to be assigned with: Bit 0 = RF 0
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// RX running, Bit 1 = RF 0 TX running, Bit 2 = RF 1 RX running, Bit 3
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// = RF 1 TX running. The configuration for each RF chain is built
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// up of the 2 bits for the RF chain (4 possible states: IDLE, RX only,
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// TX only, TX/RX).
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// </info>0
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// </value>
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// <value name="FPGA_STATE" integer="2">
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// <info>
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// The 4 bit wide ATR FPGA state is used as configuration. This enables 16 states.
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// </info>
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// </value>
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// </enumeratedtype>
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//
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// <register name="CURRENT_CONFIG_REG" size="32" offset="0x00" attributes="Readable">
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// <info>
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// Contains the current active configuration.
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// </info>
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// <bitfield name="CURRENT_RF0_CONFIG" range="7..0" type="integer">
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// <info>
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// Current active configuration for switches and LEDs of RF 0.
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// </info>
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// </bitfield>
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// <bitfield name="CURRENT_RF1_CONFIG" range="15..8" type="integer">
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// <info>
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// Current active configuration for switches and LEDs of RF 1.
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// </info>
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// </bitfield>
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// <bitfield name="CURRENT_RF0_DSA_CONFIG" range="23..16" type="integer">
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// <info>
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// Current active configuration for DSAs of RF 0.
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// </info>
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// </bitfield>
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// <bitfield name="CURRENT_RF1_DSA_CONFIG" range="31..24" type="integer">
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// <info>
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// Current active configuration for DSAs of RF 1.
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// </info>
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// </bitfield>
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// </register>
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//
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// <register name="OPTION_REG" size="32" offset="0x04" attributes="Readable|Writable">
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// <info>
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// Set the option to be used for the RF chains.
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// </info>
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// <bitfield name="RF0_OPTION" range="1..0" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
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// <info>
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// Option used for switches and LEDs of RF 0.
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// </info>
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// </bitfield>
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// <bitfield name="RF1_OPTION" range="9..8" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
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// <info>
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// Option used for switches and LEDs of RF 1.
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// </info>
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// </bitfield>
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// <bitfield name="RF0_DSA_OPTION" range="17..16" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
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// <info>
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// Option used for DSAs of RF 0.
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// </info>
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// </bitfield>
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// <bitfield name="RF1_DSA_OPTION" range="25..24" type="ATR_OPTIONS" initialvalue="SW_DEFINED">
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// <info>
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// Option used for DSAs of RF 1.
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// </info>
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// </bitfield>
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// </register>
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//
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// <register name="SW_CONFIG_REG" size="32" offset="0x08" attributes="Readable|Writable">
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// <info>
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// Contains the configuration to be applied in case SW_DEFINED option is
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// chosen.
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// </info>
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// <bitfield name="SW_RF0_CONFIG" range="7..0" type="integer" initialvalue="0">
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// <info>
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// SW defined configuration for switches and LEDs of RF 0.
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// </info>
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// </bitfield>
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// <bitfield name="SW_RF1_CONFIG" range="15..8" type="integer" initialvalue="0">
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// <info>
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// SW defined configuration for switches and LEDs of RF 1.
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// </info>
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// </bitfield>
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// <bitfield name="SW_RF0_DSA_CONFIG" range="23..16" type="integer" initialvalue="0">
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// <info>
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// SW defined configuration for DSAs of RF 0.
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// </info>
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// </bitfield>
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// <bitfield name="SW_RF1_DSA_CONFIG" range="31..24" type="integer" initialvalue="0">
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// <info>
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// SW defined configuration for DSAs of RF 1.
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// </info>
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// </bitfield>
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// </register>
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// </group>
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//</regmap>
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//XmlParse xml_off
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