miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
7e3f04d0ab96247bf805ef5b8f3d2c75a518fa63
b210-k7-fpga/top
T
History
Wade Fife 7e3f04d0ab fpga: e320: Update AXI interconnect address range 
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: d352f5a9c3bd3791f0320be1e615146fe7459453
2020-08-28 15:07:38 -05:00
..
b2xxmini
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
b200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x
fpga: e31x: Change RFNoC Ctrl clock to 40 MHz
2020-08-19 12:28:22 -05:00
e320
fpga: e320: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
n3xx
fpga: n3xx: Fix timeout for timekeeper registers
2020-08-19 12:28:22 -05:00
python
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300
fpga: remove liberio
2020-07-20 16:01:03 -05:00
Makefile.common
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00