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fpga: rfnoc: Fix testbenches to run under ModelSim

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This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.


Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
This commit is contained in:
Wade Fife
2020-07-20 15:33:22 -05:00
parent 2f517134cd
commit dce6ce8063
9 changed files with 70 additions and 91 deletions
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top/e31x/sim/e310_io_tb/Makefile
+4 -3
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@@ -25,11 +25,12 @@ DESIGN_SRCS = $(abspath ../../e310_io.v) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
SIM_TOP = e310_io_tb
# Define toplevel module
SIM_TOP = e310_io_tb glbl
SIM_SRCS = \
$(abspath e310_io_tb.sv)
$(abspath e310_io_tb.sv) \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
#-------------------------------------------------
# Bottom-of-Makefile