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fpga: Update testbenches to work in ModelSim

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Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
This commit is contained in:
Wade Fife
2021-06-17 08:16:59 -05:00
parent 162632e7c1
commit fcfc6bf387
11 changed files with 304 additions and 137 deletions
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top/n3xx/sim/dram_fifo/Makefile
+32 -3
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@@ -50,16 +50,45 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_tb.sv) \
$(abspath axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/n3xx/sim/dram_fifo_bist/Makefile
+32 -3
View File
@@ -50,16 +50,45 @@ $(IP_FIFO_4K_2CLK_SRCS) \
$(IP_FIFO_SHORT_2CLK_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/sim/axi_intercon_4x64_256_bd.v \
$(IP_BUILD_DIR)/axi_intercon_4x64_256_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_bist_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_bist_tb.sv) \
$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x300/sim/aurora_loopback/Makefile
+26 -1
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@@ -50,6 +50,30 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
$(AURORA_PHY_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi64_4k_2clk_fifo/sim/axi64_4k_2clk_fifo.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma_core.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/src/*.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/*.v \
$(IP_BUILD_DIR)/aurora_64b66b_pcs_pma/aurora_64b66b_pcs_pma/example_design/gt/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
unisims_ver \
unimacro_ver \
secureip \
fifo_generator_v13_2_4 \
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
@@ -66,7 +90,8 @@ SIM_SRCS = \
$(abspath aurora_loopback_tb.sv) \
$(SIM_GENERAL_SRCS) \
$(SIM_CONTROL_SRCS) \
$(SIM_AXI_SRCS)
$(SIM_AXI_SRCS) \
$(MODELSIM_IP_SRCS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x300/sim/dram_fifo/Makefile
+32 -3
View File
@@ -52,16 +52,45 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
$(IP_AXI4_BRAM_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/sim/axi_intercon_2x64_128_bd.v \
$(IP_BUILD_DIR)/axi_intercon_2x64_128_bd/ip/*/sim/*.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/ddr3_32bit_mig_sim.v \
$(IP_BUILD_DIR)/ddr3_32bit/ddr3_32bit/user_design/rtl/*/*.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
secureip \
fifo_generator_v13_2_4 \
axi_register_slice_v2_1_19 \
axi_infrastructure_v1_1_0 \
axi_dwidth_converter_v2_1_19 \
axi_crossbar_v2_1_20 \
blk_mem_gen_v8_4_3 \
axi_data_fifo_v2_1_18 \
generic_baseblocks_v2_1_0 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS = glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_tb.sv) \
$(abspath axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x300/sim/dram_fifo_bist/Makefile
+21 -3
View File
@@ -52,16 +52,34 @@ $(IP_FIFO_SHORT_2CLK_SRCS) \
$(IP_AXI4_BRAM_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
MODELSIM_IP_SRCS = $(wildcard $(abspath \
$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
$(IP_BUILD_DIR)/axi4_dualport_sram/sim/axi4_dualport_sram.v \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
))
MODELSIM_LIBS += \
fifo_generator_v13_2_4 \
blk_mem_gen_v8_4_3 \
modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
MODELSIM_ARGS += glbl -t 1fs
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
SIM_TOP = dram_fifo_bist_tb
SIM_SRCS = \
SIM_SRCS += \
$(abspath dram_fifo_bist_tb.sv) \
$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
$(IP_DDR3_32BIT_SIM_OUTS)
$(IP_DDR3_32BIT_SIM_OUTS) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x400/ip/eth_100g_bd/lbus_tb/Makefile
+1 -1
View File
@@ -25,6 +25,7 @@ include $(BASE_DIR)/../lib/fifo/Makefile.srcs
#$(abspath ../../../build-ip/xczu28drffvg1517-1e/eth_100g_bd/eth_100g_bd/ip/eth_100g_bd_cmac_usplus_0_0/eth_100g_bd_cmac_usplus_0_0/example_design/eth_100g_bd_cmac_usplus_0_0_axis2lbus_segmented_top.v) \
DESIGN_SRCS = $(abspath \
$(abspath ../PkgEth100gLbus.sv) \
$(abspath ../eth_100g_axis2lbus.sv) \
$(abspath ../eth_100g_lbus2axis.sv) \
$(FIFO_SRCS) \
@@ -41,7 +42,6 @@ TB_TOP_MODULE ?= lbus_all_tb
SIM_TOP = $(TB_TOP_MODULE)
SIM_SRCS = \
$(abspath ../PkgEth100gLbus.sv) \
$(abspath axi_lbus_tb.sv) \
$(abspath lbus_axi_tb.sv) \
$(abspath $(TB_TOP_MODULE).sv) \
top/x400/sim/x4xx_qsfp_wrapper/Makefile
+87 -74
View File
@@ -9,12 +9,9 @@
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../top)
IP_DIR = $(BASE_DIR)/x400/ip
# Include viv_sim_preamble after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
IP_BUILD_DIR = $(BASE_DIR)/x400/build-ip/xczu28drffvg1517-1e
#-------------------------------------------------
# Design Specific
@@ -24,106 +21,122 @@ ARCH = zynquplusRFSOC
PART_ID = xczu28dr/ffvg1517/-1/e
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/control/Makefile.srcs
include $(BASE_DIR)/../lib/axi/Makefile.srcs
include $(BASE_DIR)/../lib/axi4_sv/Makefile.srcs
include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
include $(BASE_DIR)/../lib/axi4lite_sv/Makefile.srcs
include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
include $(BASE_DIR)/../lib/xge/Makefile.srcs
include $(BASE_DIR)/../lib/wb_spi/Makefile.srcs
include $(BASE_DIR)/../lib/fifo/Makefile.srcs
include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
include $(BASE_DIR)/../lib/xge/Makefile.srcs
include $(IP_DIR)/Makefile.inc
IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
sim/axi_eth_dma_bd.v\
ip/*/sim/*.h\
ip/*/sim/*.v\
ip/*/sim/*.vhd\
ip/*/bd_0/hdl/*.v\
ip/*/bd_0/sim/*.v\
ip/*/bd_0/ip/ip_*/sim/*.v\
ip/*/bd_0/ip/ip_*/sim/*.sv\
ip/*/bd_0/ip/ip_*/sim/*.vhd\
ipshared/*/hdl/*.sv\
ipshared/*/hdl/*.v\
ipshared/*/simulation/*.v\
ipshared/*/hdl/verilog/*.v\
ipshared/*/hdl/verilog/*.svh\
ipshared/*/hdl/verilog/*.vh\
))
IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
ip/*/sim/*.v\
))
TOP_SRC = \
$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv) \
$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv) \
$(abspath $(BASE_DIR)/x400/x4xx_mgt_io_core.sv) \
$(abspath $(BASE_DIR)/x400/x4xx.v)
# Xilinx IP wants lots of libraries
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
VLOG_ARGS = +define+SIM_SPEED_UP
SVLOG_ARGS = -lint +define+BUILD_100G=1
# Xilinx IP wants a second file loaded
MODELSIM_ARGS = glbl -t 1fs
DESIGN_SRCS = $(abspath \
DESIGN_SRCS += $(abspath \
$(AXI4_SV_SRCS) \
$(AXI4S_SV_SRCS) \
$(AXI4LITE_SV_SRCS) \
$(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) \
$(AXI_SRCS) \
$(XGE_SRCS) \
$(XGE_INTERFACE_SRCS) \
$(PACKET_PROC_SRCS) \
$(RFNOC_UTIL_SRCS) \
$(RFNOC_XPORT_SRCS) \
$(RFNOC_XPORT_SV_SRCS) \
$(RFNOC_XBAR_SRCS) \
$(RFNOC_CORE_SRCS) \
$(WISHBONE_SRCS) \
$(XGE_SRCS) \
$(XGE_INTERFACE_SRCS) \
)
# Add files for the DUT
DESIGN_SRCS += $(abspath \
$(BASE_DIR)/x400/x4xx_mgt_io_core.sv \
$(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv \
$(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv \
)
#-------------------------------------------------
# IP Specific
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory
IP_DIR = ../../ip
# Include makefiles and sources for all IP components
# *after* defining the IP_DIR
include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc
include $(IP_DIR)/xge_pcs_pma/Makefile.inc
include $(IP_DIR)/eth_100g_bd/Makefile.inc
DESIGN_SRCS += $(abspath \
$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \
$(IP_AXI_ETH_DMA_BD_HDL_SRCS) \
$(IP_AXI_ETH_DMA_BD_SRCS) \
$(XGE_PCS_PMA_SRCS) \
$(IP_100G_HDL_SRCS) \
$(IP_100G_BD_SRCS) \
)
#-------------------------------------------------
# ModelSim Specific
#-------------------------------------------------
IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
sim/axi_eth_dma_bd.v \
ip/*/sim/*.h \
ip/*/sim/*.v \
ip/*/sim/*.vhd \
ip/*/bd_0/hdl/*.v \
ip/*/bd_0/sim/*.v \
ip/*/bd_0/ip/ip_*/sim/*.v \
ip/*/bd_0/ip/ip_*/sim/*.sv \
ip/*/bd_0/ip/ip_*/sim/*.vhd \
ipshared/*/hdl/*.sv \
ipshared/*/hdl/*.v \
ipshared/*/simulation/*.v \
ipshared/*/hdl/verilog/*.v \
ipshared/*/hdl/verilog/*.svh \
ipshared/*/hdl/verilog/*.vh \
))
IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
sim/*.v \
ip/*/sim/*.v \
))
MISC_IP_SIM_SRCS += \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
$(abspath $(IP_BUILD_DIR)/xge_pcs_pma/model_10gbe.sv) \
DESIGN_SRCS += $(abspath \
$(IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS) \
$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
$(IP_AXI_ETH_DMA_BD_HDL_SRCS) \
$(IP_100G_HDL_SRCS) \
$(AURORA_PHY_SRCS) \
$(IP_HDL_SIM_SRCS) \
$(TOP_SRC) \
$(IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS) \
$(IP_100G_HDL_SIM_SRCS) \
$(IP_XGE_PCS_PMA_HDL_SIM_SRCS) \
$(MISC_IP_SIM_SRCS) \
)
# Xilinx IP wants lots of libraries
MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
MODELSIM_ARGS += glbl -t 1fs
# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
VLOG_ARGS += +define+SIM_SPEED_UP
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS += -suppress 2583
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
# Define only one top-level module
TB_TOP_MODULE ?= x4xx_qsfp_wrapper_all_tb
SIM_TOP = $(TB_TOP_MODULE)
SIM_SRCS = \
$(abspath x4xx_qsfp_wrapper_tb.sv) \
$(abspath $(TB_TOP_MODULE).sv)
# Suppressing the following worthless reminder.
#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
SVLOG_ARGS = -suppress 2583
$(abspath $(TB_TOP_MODULE).sv) \
#-------------------------------------------------
# Bottom-of-Makefile
top/x400/sim/x4xx_qsfp_wrapper/x4xx_qsfp_wrapper_tb.sv
+2 -2
View File
@@ -154,8 +154,8 @@ module x4xx_qsfp_wrapper_tb #(
AxiLiteIf_v #(.DATA_WIDTH(32),.ADDR_WIDTH(40))
s_axi_v (clk40, clk40_rst);
`include "../../../../../../lib/axi4lite_sv/axi_lite.vh"
`include "../../../../../../lib/axi4_sv/axi.vh"
`include "../../../../lib/axi4lite_sv/axi_lite.vh"
`include "../../../../lib/axi4_sv/axi.vh"
always_comb begin
`AXI4LITE_ASSIGN(s_axi_v,s_axi)
axi_hp_v.arready = 1'b1;