The address ranges configured for the AXI interconnect IP limited the
amount of accessible DRAM to two 32 MB regions. This change makes the
full 1G available to all DRAM ports.
Original-commit: bba0cddfadcb744e8a6fae27d57ba8d3995eaf64
This updates the chdr_to_axis method so that it doesn't change the
input chdr_packet object. This is useful in case there are other
references to that object in use. Not modifying the object means that
you don't always have to copy the object before passing it to this
method.
Original-commit: 259506c4993834d9ef8ccb48635623552b075237
The axis_data_to_chdr block previously only sampled the sideband
information at the end of the packet. This adds a parameter that
controls if the sideband information should be sampled at the beginning
of the packet or the end of the packet. In the former case, large
internal packet buffers are not required.
Original-commit: a8c4f021277cf3b0a0897fa9da0252541512f3a6
Add -voptargs=+acc to the default options when running vsim. This
option enables debug command access to objects in the design, which is
generally needed for debugging in the GUI.
Original-commit: eed2d2348cab7dc786673f0649373809d04027d5
The axis_split module takes a single AXI-Stream input and duplicates it
onto multiple AXI-Stream outputs. This block correctly handles the
somewhat tricky flow-control logic so that the AXI-Stream handshake
protocol is honored at all top-level ports.
Original-commit: fa0f4b2833119d57d331f592028ff9f032895c89
Xilinx changed the way [all_registers -edge_triggered] is treated such
that set_max_delay constraints that use it can cause segmentation and
cause clocks to not be propagated to all endpoints. Changing to
[all_ffs] avoids this potential issue.
Original-commit: 55e422535292c29de00b80f15b0a49ca3fb94f26
Xilinx changed the default Vivado install location from /opt/Xilix to
/tools/Xilinx. This commit adds support for finding Vivado in either
the new location or the old location.
Original-commit: 156d714b8fb288100d242ea200ae1d1dcd6bcd57
This adds the "modelsim" simulator option to run_testbenches.py to allow
for regression testing of the native ModelSim simulation target.
Original-commit: 39d6007ca7e3b27e8230db6690faa7469ca62cb2
For example, the ChdrPacket typedef is being renamed from ChdrPacket to
ChdrPacket_t. This allows the code to distinguish between the
unparameterized class and the already parameterized class. This isn't
strictly necessary, but it makes some Vivado 2019.1 bugs easier to work
around. It also makes the code slightly less ambiguous.
Original-commit: df27e9fa05d2d767f69182763852f6803c5b2a34
This adds variants of the send and recv methods in RfnocBlockCtrlBfm
and ChdrIfaceBfm that input/output items instead of CHDR words.
Original-commit: aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6
This replaces chdr_word_t, which was a statically defined 64-bit data
type, with a paramaterizable data type that matches the defined CHDR_W.
Code that formerly referenced the chdr_word_t data type can now define
the data type for their desired CHDR_W and ITEM_W as follows:
// Define the CHDR word and item/sample data types
typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t;
ITEM_W is optional when defining chdr_word_t if items are not
needed. Static methods in the ChdrData class also provide the ability to
convert between CHDR words and data items. For example:
// Convert CHDR data buffer to a buffer of samples
samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
Original-commit: fc895feacb8dde3b02c9a4eccb4b4f4a654f2881
This eliminates the complicated semaphore from the testbench and brings
the radio testbench in line with the other testbenches.
Original-commit: 8727642de2aa22e982e012d85d32325f664a3e9e
Wade Fife