This change sets StdArithNoWarnings and NumericStdNoWarnings by
default for ModelSim simulations. Without this, an excessive number of
warnings can be generated by Xilinx IP during simulation.
Original-commit: f094aa7ae0f864764276c5c67c51b21547327fb0
This changes the -onfinish setting from "stop" to "final" for Questa
and ModelSim. The "final" setting is required so that SystemVerilog
final blocks run. This also has the same effect as "stop" in that it
won't ask you in the GUI if you want to exit the simulator when
$finish() is called.
Original-commit: 7ab4e9a4e2c0408ca595ad168199a54bf416c894
This commit addresses several issues that can occur with different
simulators. It changes the following:
- Update documentation
- Ignore testbenches in build-ip folders
- Tolerate extra lines in the testbench results regular expression
- Match numbers using \d instead of + to avoid ValueError exceptions
- Only fetch the start_time if it exists
- Allow any simulator make target (don't limit it to specific choices)
Original-commit: 81ccd8cb5154e85636cddd86c466daffb4ab4ebe
This adds the NIPC parameter, which configures support for processing
multiple items or samples per clock cycle. With this enabled, the FFT
block can process at rates higher than 250 MSPS, such as 500 MSPS and
beyond.
Original-commit: fc76aa940e121fe1f85a3513f6d90df4667338cf
On the CPU to Ethernet path (c2e) in some configurations the trailing
bytes length was not being properly set in TUSER. This can lead to
extra bytes being added onto packets. Most of the time this is fine,
since the extra bytes would be ignored by the underlying protocols.
But when the packet was near the MTU size, it could lead to an
oversized packet that would get dropped by the network or host
computer.
Original-commit: 00d9a228f58b384798f0a1346fbab8f40b017a9c
This wrapper was using TUSER for the number of trailing bytes, but it
wasn't properly enabled, which could cause it to be ignored in some
cases.
Original-commit: e7ebe601163d01d157bc3de9c2652952932e4a1c
This was set to 1 in UHD 4.7, but it must be 2 for all channels to
have sufficient bandwidth.
Original-commit: b012c18fd653714e84b1d4a86e27ff90fe13ae04
Fixed an issue where the DDC could experience an arithmetic overflow
when receiving a full-scale signal with non-zero DDS frequency.
Original-commit: 5030d0106b6d2230a1c28e72f765098c7916cf1b
This reverts commit e572bab3ee5aa40f57bdc6e11d6381cad1d1401a.
The problem with skipping the "unnecessary" bash wrappers is that Ubuntu
systems use 'dash' as a default shell, which does not support our build
infrastructure. While we do recommend not using dash for building FPGA
builds in our documentation, it's not obvious that dash is the problem
when calling rfnoc_image_builder.
Original-commit: 888850d6417c93f561e0555c693e3f11e9f40856
Radio command FIFO will back pressure commands until there is room
for new elements.
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 474a17020e649e9ae4a39ef7cbce810d0ec67983
Remove unused stall_probability arguments from
get_master_stall_prob() and get_slave_stall_prob().
Original-commit: 80db09235b5fa0cd4259c80c3a094435b519a752
Together with an update to the LMK04832 register config according to
TIs data sheet, all clock outputs are now aligned to SYSREF rising edge.
Therefore, I needed to adjust the SYSREF capture mechanism inside the
RFSoC and the SYSREF LMK Delay.
SYSREF is now captured first at the falling edge of PRC.
To be on the safe side, we are still double synchronizing SYSREF
afterwards on the rising edges of PRC.
As we are now independent of any MCR regarding timing constraints the
SYSREF Delay is also set to '0' for all X4xx devices.
Original-commit: b5cb4fac42ab530174e108455b730ffa1510d70a
In cases when the info FIFO fills, it was possible for
in_pkt_info_tvalid to be asserted then on the next cycle
in_pkt_info_tready would deassert, in which case the input would be
dropped. This change ensures that tvalid remains asserted until tready
deasserts.
Original-commit: 6d2e9f983ae94d2e1e6866c34b3c87374a349631
The TX radio will normally transmit a late not-timed packet when an
underflow occurs between packets within a burst. However, if it was
only one cycle late, then the packet would be dropped. This change
rearms the state machine more quickly in this corner case to allow
this late packet to be accepted. The underflow error will still be
reported.
Original-commit: 9faac6597cf21ca11e40d4e98797cea2848c40b0
This Python utility was getting a bit rotten. The following updates
where made:
- Reformatted using ni-python-styleguide
- Fixed formatting of regex strings by declaring them 'raw'
- Updated docstrings and any linter issues
On Pyton 3.12 and beyond, this will no longer throw SyntaxError
warnings.
Original-commit: 0dede88c6535ae6ffb30b162c83dc01d59d3bfa0
Previously, the build tools for the FPGA bitfiles would try and
autodetect the Vivado executable, but would allow for a `vivado_lab`
executable. However, Vivado Lab Edition can't build bitfiles nor run
testbenches. Its only use with the USRP FPGA build tooling is to run
`viv_jtag_program` and `viv_jtag_list` (which are command-line proxies
for probing FPGAs attached to JTAG, and for programming bitfiles over
JTAG, e.g. to an X3x0).
When Vivado Lab and Vivado were present, it was possible that we ran
into issues where Vivado Labs would be preferred, and then builds or
testbenches would fail.
We therefore remove the ability to use Vivado Lab. Running the Vivado
Lab Edition with the GUI, and loading and probing bitfiles is of course
still possible, but tools like `rfnoc_image_builder` can no longer
accidentally try to use Vivado Lab instead of regular Vivado.
Original-commit: 21c4c591a51d520c7aac7108e853e59c4953f953
Max Köhler