Wade Fife f19fa3cf82 fpga: rfnoc: Fix info FIFO overflow ...

In cases when the info FIFO fills, it was possible for
in_pkt_info_tvalid to be asserted then on the next cycle
in_pkt_info_tready would deassert, in which case the input would be
dropped. This change ensures that tvalid remains asserted until tready
deasserts.


Original-commit: 6d2e9f983ae94d2e1e6866c34b3c87374a349631

2025-02-11 12:30:50 -06:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fpga: rfnoc: Fix info FIFO overflow

2025-02-11 12:30:50 -06:00

sim

fpga: sim: Initialize test_status

2024-06-20 11:35:27 +02:00

tools

fpga: tools: Refactor viv_ip_xci_editor.py

2025-02-07 14:52:28 +01:00

top

fpga: x400: avoid false PPS rising edge on switching sources

2025-02-05 16:56:54 -06:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

No description provided

84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%