Any packet less than CUT_THROUGH bytes has a high chance of getting
stuck in the TX FIFO of the xge_mac_wrapper. In cut-through mode we
were waiting for CUT_THROUGH bytes before transmitting the packet.
Original-commit: 1938bb951a981f4d3016b796f771b5047fb846a2
When operating in cut-through mode the hold off from the MAC was not
applying back pressure, so when the TX interface filled up, data was
dropped. This bug was introduced when cut-through was added, and does
not impact the original implementation.
Original-commit: 6cd9662e2b8f2e159805015f3dd9087089a454af
- Detect dropped words at the dispatch level. This prevents
an overflow on CHDR from block CPU.
- Dropped packets are recorded as CPU or CHDR drop count
- Refactor to put chdr_xport_adapter.sv in different clock
domain to improve timing
- Unwrinkle tkeep/trailing transitions
Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
- Made some things optional to reduce logic when
used with the new xport_sv:
(1) Clocking to sys_clk
(2) Preamble insertion
- New options to CUTTHROUGH faster on the TX path.
The new xport_sv already has a gate to accumulate at
its clock crossing.
Original-commit: a68e7101167a4b5bf7b60ed90d963982aae735b8
Consolidated calcuation of last_tkeep and tkeep_last. Changed error
checking to support unwrinkling tkeep/trailing changes in 100G
etherent and support for testing packet dropping on backup.
Original-commit: 473b0f5abe882ca316a7fe1a59234676940ef26b
AxiLiteBfm incorrectly included stb argument on rd() and printed actual
response instead of expected in debug message.
Original-commit: cb7e9e24578ccf4db79878a7437a6a85ad315ee2
This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that
can be used to stitch onto Verilog port_maps.
Original-commit: 6ef642e3ac44c52b98b124f30dc84b1683859989
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
Contains a fix for the AXI4LITE_ASSIGN macro, and adds
AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and
AXI4LITE_DEBUG_ASSIGN macros.
Original-commit: c718faf3387a07a9a1b86ab473f6ed7ac4cb493a
Components are connected together with AxiStreamIfc. Some features
include:
(1) Add bytes to the start of a packet
(2) Remove bytes from a packet
(3) Wrappers for some older components
a. fifo - buffer but imediately pass a packet
b. packet_gate - buffer and hold till end of packet
c. width_conv - cross clock domains and change width of axi bus
The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
- reached_packet_byte - notify when tdata contains a paritcular byte
- get_packet_byte/get_packet_field - extract a byte or field from axi
- put_packet_byte/put_packet_field - overwrite a byte or field onto axi
Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
and an AxiLiteBfm class.
Important Methods
a. wr - performs non-blocking write and checks for expected response
b. wr_block - performs a blocking write and provides response
c. rd - performs a non-blocking read and checks for expected response
d. rd_block - persforms a blocking read and provides response
The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods. When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.
Original-commit: afee1888dd7c2d9d95e537f505ce7ab36252763a
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.
Used in xport when calculating new UDP headers for CHDR traffic.
Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.
Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.
Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600
This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.
Adds or modifies the following simulation make targets:
make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim
Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS - Added to SystemVerilog invocation of vlog
VLOG_ARGS - Added to Verilog invocation of vlog
VHDL_ARGS - Added to VHDL invocation of vcom
Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e
Andrew Moch