Commit Graph
21 Commits
Author SHA1 Message Date
michael-west 0971ae69cb Replay buffered TX streamer: Fix gaps in TX
Gaps in transmission were seen when using the replay buffered TX
streamer caused by the Replay block setting the end of burst flag at the
end of every send() call.  This fix adds a flag to the Replay block play
command register to avoid setting the end of burst flag and modifies the
replay buffered TX streamer to use the flag based on the metadata passed
in to the send() call.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 2419f405775934efa517e025929356ef0a0d181e
2023-04-06 15:34:46 -05:00
michael-west 4b6d01bf54 fpga: Reformat javascript in doc
The long lines were causing Debian lintian failures, so they have been
reformatted.  No functional changes.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1b6c6d12fff4a6152595418a2ad54396ad8ae1f9
2023-02-10 11:48:12 -08:00
michael-west 2c0fea5d1e fpga: Update copyright
Update copyright on recently changed files.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 92c09f7f766586683ebd67bb3a57005250c4d81d
2023-01-19 15:55:56 -08:00
michael-west a79dc444a3 FPGA: Fix overflows in DDC
Added proper clipping of halfband filter output to handle potential
overflow.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: b2d4eaa8e59110e39ca691187f66a07953bdd0d2
2023-01-19 10:05:27 -06:00
michael-west b8163da1d1 FPGA: Restore FIR filter in rx_frontend_gen3
The FIR filter applied gain.  Removing it caused incorrect scaling and
signals where every other sample was zero.  Also parameterized heterodyne
frontend processing so it would not use resources in images not
requiring it.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
2023-01-19 10:05:27 -06:00
michael-west 740202aa22 FPGA: Fix warnings in dds_freq_tune module
Added missing tuser connections.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: e3ffef975db464fb8d78f411c6fa0ad71f8e9b41
2023-01-19 10:05:27 -06:00
michael-west 5309c96f80 rfnoc: Fix test_timed_commands for RFNoC devices
- Added command time to readback of time from Radio block.
- Added wait for time to readback of shared registers in Radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 8daa80c05f8006697aea05fea4ac5cd4dabbaef1
2022-04-05 13:18:09 -07:00
michael-west 1c5b744a4d FPGA: Replay block version 1.1
- Add registers to read current record and  play positions.
- Add register to read current space in play command FIFO to allow
  software to avoid overflowing the FIFO.
- Cache base address and size with play command in command FIFO.
- Fix timestamp logic.  Timestamp is only for the first packet of a
  burst.  The increment of 1 for each sample is not accurate because
  it assumed the Replay block was playing at the same rate as the
  Radio, which cannot be assumed.

Maintained backwards compatibility with older API.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1545d3ff05f14b8dd175736b326fe6cae7dc830d
2022-04-01 13:33:08 -07:00
michael-west 29ab52420f fpga: rfnoc: Fix PPS edge detection
Make timekeeper module sample rising edge instead of falling edge of PPS
signal.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: b6c7e99830f10c21262247cafa3e077fe3f54119
2022-03-09 17:49:38 -06:00
michael-west c4cd0a129d fpga: Add ability to get time from Radio block
Added registers to read back radio time.  Bumped minor compat.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 43ab4c8b43d8407fc9f345ca4b13634f03ad4a43
2021-11-17 08:56:39 -06:00
michael-west 5983927439 sim: Update chdr_16sc_to_sc12 testbench
Modified to send 2 packets back to back at each packet size to test
output during sequential input packets.  Also fixed whitespace.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9
2021-08-10 15:19:32 -05:00
michael-west 946ff5574d fpga: Re-order error and data packets
Added delay to error packets so overrun error is back in-band.  Avoids
dropping good data packets in the case of an overrun.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: a69e6fcdc79dfa1ea48c99092b6edb9633b6fb24
2021-08-10 15:19:32 -05:00
michael-west 8332f5b161 fpga: Fix sc16 to sc12 converter
Re-wrote converter to remove clock cycle delay on i_tready when handling
residual output and fixed improper handling of tlast during residual
data processing.  Resolves some USB overflow issues when using sc12 data
type on B200 devices.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 1fecf446e0358aa2b6a2d1f73a0daeac516435a0
2021-08-10 15:19:32 -05:00
michael-west 8164e94fbd N3xx: Fix White Rabbit
Reconnect the signals from the White Rabbit module to the TDC in the
FPGA.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c0637bae1e4a0ddb996cf2b7eadfad22f782874b
2021-08-04 15:19:58 -05:00
michael-west 4fa8a41e0b TwinRX: Remove frontend filter
Removing the FIR filter in the frontend to reclaim resources and remove
redundancy when using a DDC block.  The default image has a DDC block,
so only users making custom RFNoC images and using TwinRX will need to
take care to properly downconvert the full bandwidth coming from the
radio block.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: ad533eb6416c76d2a986c97fff846785ee56567e
2021-04-08 08:48:18 -05:00
michael-west bb7e7023e6 E320: Revert addition of Replay block
The DMA FIFO is needed for DDR3 BIST, so it is being restored for now.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 413ebee61254fd0b9ab0cd11b475b8a849579cd8
2020-09-04 15:45:51 -07:00
michael-west 4c7ee1eb8e TwinRX: Fix increased noise floor
- Fixed bus width from 25 to 24 bits

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: fdd576cda1bab000745af66e565f4eb8c6272942
2020-07-21 11:47:20 -05:00
Michael West 8556184025 TwinRX: Remove decimation from frontend
The decimation in the rx_frontend_gen3 was added to reduce the bandwidth
between the Radio and the DDC due to the limitation in bandwidth over
the crossbar for dynamically connected blocks.  The default FPGA image
for the X300 now has a static connection between the Radio and DDC, so
this is no longer necessary.

This change allows the TwinRX receive channels to be time aligned with
channels from other daughterboards so they can be used in the same
streamer.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: d0c162bc7a4ac82f6104506b17d7be05e1780336
2020-05-12 12:03:31 -05:00
Michael West dc86b52fd7 DUC/DDC: Add variable time increment
Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample.  Defaults to legacy behavior.

Minor compat number bumped on DUC and DDC blocks.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62
2020-05-12 12:03:31 -05:00
Michael West 45d274746f X300: Make VITA time monotonic
Make timekeeper tick on every cycle of the radio clock.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: 7886b71f13e9f6e5786c95286ef98f49ab716119
2020-05-12 12:03:31 -05:00
michael-west bd647a7a8d Adding bootram.coe file from latest firmware changes.
Original-commit: 973b47c48339dbae2e125a8c8d84ef67fedc4bdf
2014-03-03 13:04:25 -08:00