bd647a7a8d2b2a6c015be65c5caa777ef0a0e5c2
Original-commit: 973b47c48339dbae2e125a8c8d84ef67fedc4bdf
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%