michael-west a79dc444a3 FPGA: Fix overflows in DDC ...

Added proper clipping of halfband filter output to handle potential
overflow.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: b2d4eaa8e59110e39ca691187f66a07953bdd0d2

2023-01-19 10:05:27 -06:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

FPGA: Fix overflows in DDC

2023-01-19 10:05:27 -06:00

sim

fpga: sim: Fix typo in clk_wait_f

2022-12-19 08:57:18 -06:00

tools

fpga: tools: Fix error detection in run_testbenches.py

2023-01-09 15:40:17 -06:00

top

FPGA: Restore FIR filter in rx_frontend_gen3

2023-01-19 10:05:27 -06:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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