michael-west b8163da1d1 FPGA: Restore FIR filter in rx_frontend_gen3 ...

The FIR filter applied gain.  Removing it caused incorrect scaling and
signals where every other sample was zero.  Also parameterized heterodyne
frontend processing so it would not use resources in images not
requiring it.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13

2023-01-19 10:05:27 -06:00

..

b2xxmini

fpga: b2xx: Generate utilization report files

2022-02-10 11:35:47 -07:00

b200

fpga: b2xx: Generate utilization report files

2022-02-10 11:35:47 -07:00

e31x

fpga: Require AR76780 for X3xx and E3xx

2022-09-23 15:09:35 -05:00

e320

fpga: e320 Change MIG arbitration to RD_PRI_REG

2022-11-08 08:20:48 -06:00

n3xx

FPGA: Restore FIR filter in rx_frontend_gen3

2023-01-19 10:05:27 -06:00

python

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

x300

FPGA: Restore FIR filter in rx_frontend_gen3

2023-01-19 10:05:27 -06:00

x400

fpga: x400: Bump FPGA compat to 7.9

2022-08-29 17:01:45 -05:00

Makefile.common

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00