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michael-west b8163da1d1 FPGA: Restore FIR filter in rx_frontend_gen3 
The FIR filter applied gain.  Removing it caused incorrect scaling and
signals where every other sample was zero.  Also parameterized heterodyne
frontend processing so it would not use resources in images not
requiring it.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
2023-01-19 10:05:27 -06:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dboards
fpga: n3xx: Cleanup MTU parameters
2022-09-01 14:41:55 -05:00
doc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dts
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
ip
fpga: Use AR76780 patch for fir_compiler
2022-08-25 13:55:30 -05:00
sim
fpga: n3xx: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_n3xx.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: n3xx: Remove unused USE_REPLAY parameter
2022-09-01 14:41:55 -05:00
Makefile.n3xx.inc
fpga: n3xx: Support advanced transport adapter
2022-08-29 17:01:45 -05:00
mb_clocks.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_timing.xdc
fpga: n3xx: Fix async clocks relationship
2022-08-25 13:55:30 -05:00
n3xx_clocking.v
fpga: n3xx: Fix clock frequency comments
2022-03-26 21:52:26 -05:00
n3xx_core.v
fpga: n3xx: Cleanup MTU parameters
2022-09-01 14:41:55 -05:00
n3xx_db_fe_core.v
FPGA: Restore FIR filter in rx_frontend_gen3
2023-01-19 10:05:27 -06:00
n3xx_mgt_channel_wrapper.v
fpga: n3xx: Cleanup MTU parameters
2022-09-01 14:41:55 -05:00
n3xx_mgt_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_wrapper.v
fpga: n3xx: Cleanup MTU parameters
2022-09-01 14:41:55 -05:00
n3xx_serial_dac_arb.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_serial_dac.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr_top.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_bist_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_bist_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_bist_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n300_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n300_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n310_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_bist_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_bist_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_bist_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n310_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n310_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n320_bist_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_bist_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_bist_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n320_bist_static_router.hex
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
n320_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
n320_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
setupenv.sh
fpga: Use AR76780 patch for fir_compiler
2022-08-25 13:55:30 -05:00
WrapBufg.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00