Michael West dc86b52fd7 DUC/DDC: Add variable time increment ...

Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample.  Defaults to legacy behavior.

Minor compat number bumped on DUC and DDC blocks.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62

2020-05-12 12:03:31 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

DUC/DDC: Add variable time increment

2020-05-12 12:03:31 -05:00

sim

fpga: sim: Don't affect packet arguments in chdr_to_axis

2020-05-04 23:40:25 -05:00

tools

fpga: tools: Add -voptargs=+acc to ModelSim GUI

2020-04-14 16:37:43 -05:00

top

X300: Make VITA time monotonic

2020-05-12 12:03:31 -05:00

.gitignore

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build.py

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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