Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ab93cb0929b9536b6d6cbfdc4813e6ba169053ae
Adds a 266.667 MHz compute engine clock and uses it instead of the
radio clock for the DDC and DUC. Using a faster clock than the radio
allows the DDC and DUC to drain after a stall in the data flow.
Original-commit: ff55d406a02cc934a5c238d22c836bea08ade3d1
FPGA:
- Split up MB registers that control daughterboard specific settings so
that daughterboards 0 and 1 could have different setings, in
preparation for future devices that require different settings.
This requires a compat number bump to 8.0.
- Add registers for additional RFDC information, including the
block/tile mapping of the individual channels, and information about
resampling capabilities
- Identify sections of code that would be specific to X410/ZBX and move
them to their own headers, so it's trivial to add device-specific
sections of code instead for other devices in the future.
- This includes constraints for clocks and I/O pins.
- Remove ability to do timed ctrlport transactions to the MB CPLD, this
was unused and possibly broken.
- Move daughterboard-specific code into its own code location
(dboards/zbx)
- Move X410-specific register documentation to its own location
(doc/X410)
- Refactor Makefiles to split out X410/ZBX specific components and allow
switching between device types
- Add 512-bit AXI interconnects
- Make number of timekeepers configurable (X410 keeps the single
timekeeper)
MPM:
- Required compat is bumped to 8.0
- Now supports new registers for detecting DSP capabilities and
multi-rate settings for the daughterboards
- Adds MMCM controls (currently unused)
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Ryan Marlow <ryan@lmarlow.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
The frontend synchronization upon time change was removed, but is
required to synchronize the RX frontend modules when sharing LOs on
TwinRX. This change restores the behavior.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c70b479007ab9f578577dfb5c2de6660e877d9a3
Moves X4C_100, X4C_200, C1_100, and C1_200 from experimental to
available targets and makes the needed changes to allow them to build
successfully.
Adds support for "UC" FPGA variant. U indicates that QSFP0 is unused
and C indicates that QSFP1 is 100 GbE.
Adds experimental CG_200 variant.
Original-commit: cb9609c886b156e22ae9d879fffad8d060f2ca2d
Removes the CPU_W parameter from x4xx.v and the qsfp_wrapper files. The
value of this parameter depends on the axi_eth_dma IP and therefore
should not be changed.
Original-commit: 84c49f40adc980e2968a6a844b4bdbb2d2d38c9c
The long lines were causing Debian lintian failures, so they have been
reformatted. No functional changes.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: 1b6c6d12fff4a6152595418a2ad54396ad8ae1f9
Adds a BUILD_BASE_DIR makefile variable that allows you to specify the
base directory for FPGA build outputs. This allows you to put the
output from each run of make into a unique directory, or to run
multiple instances of make in parallel with each build's output being
put in a different directory. For example:
make X310_XG BUILD_BASE_DIR=/path/to/builds
Original-commit: bc6db8409ba756bbad0d0c158ffb00c614b58fd9
Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.
For example, you could run the following to produce an FPGA build with
different timing results from the default build:
make X310_XG BUILD_SEED=123
Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
The FIR filter applied gain. Removing it caused incorrect scaling and
signals where every other sample was zero. Also parameterized heterodyne
frontend processing so it would not use resources in images not
requiring it.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
- Bump firmware compat to 6.1
- Remove crossbar counter logic (the FPGA does *not* support crossbar
counters anymore, so we remove it from the firmware as well)
- Remove crossbar programming control (this is now provided by RFNoC
management packets)
- Remove UDP framing control (this is also provided by RFNoC management
packets)
- Remove Ethernet link/activity LED control (this has been handled by
the FPGA directly for years now)
- Add functionality to program transport adapter. The TA is programmed
directly on the settings bus, so for the most part, this is already
possible from the firmware. The only exception is the 'virtual'
register to program IP address and MAC at the same time. In the
firmware, it will perform an ARP lookup of the MAC address, and then
write the "normal" IPv4 address register in the TA, as well as the MAC
address registers.
- Updated bootram.coe
Original-commit: 89fb75288e151cd1e43af765618c0665e79801f9
Patch AR76780 was already listed as a requirement for X4xx and N3xx,
but was not listed as a requirement for X3xx and E3xx. This change
makes it required for all Vivado-based USRPs.
Original-commit: 5aa6bc4418a30d6e6fde80b80632f9f9115ea5c4
Wade Fife