This was set to 1 in UHD 4.7, but it must be 2 for all channels to
have sufficient bandwidth.
Original-commit: b012c18fd653714e84b1d4a86e27ff90fe13ae04
Fixed an issue where the DDC could experience an arithmetic overflow
when receiving a full-scale signal with non-zero DDS frequency.
Original-commit: 5030d0106b6d2230a1c28e72f765098c7916cf1b
This reverts commit e572bab3ee5aa40f57bdc6e11d6381cad1d1401a.
The problem with skipping the "unnecessary" bash wrappers is that Ubuntu
systems use 'dash' as a default shell, which does not support our build
infrastructure. While we do recommend not using dash for building FPGA
builds in our documentation, it's not obvious that dash is the problem
when calling rfnoc_image_builder.
Original-commit: 888850d6417c93f561e0555c693e3f11e9f40856
Radio command FIFO will back pressure commands until there is room
for new elements.
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Original-commit: 474a17020e649e9ae4a39ef7cbce810d0ec67983
Remove unused stall_probability arguments from
get_master_stall_prob() and get_slave_stall_prob().
Original-commit: 80db09235b5fa0cd4259c80c3a094435b519a752
Together with an update to the LMK04832 register config according to
TIs data sheet, all clock outputs are now aligned to SYSREF rising edge.
Therefore, I needed to adjust the SYSREF capture mechanism inside the
RFSoC and the SYSREF LMK Delay.
SYSREF is now captured first at the falling edge of PRC.
To be on the safe side, we are still double synchronizing SYSREF
afterwards on the rising edges of PRC.
As we are now independent of any MCR regarding timing constraints the
SYSREF Delay is also set to '0' for all X4xx devices.
Original-commit: b5cb4fac42ab530174e108455b730ffa1510d70a
In cases when the info FIFO fills, it was possible for
in_pkt_info_tvalid to be asserted then on the next cycle
in_pkt_info_tready would deassert, in which case the input would be
dropped. This change ensures that tvalid remains asserted until tready
deasserts.
Original-commit: 6d2e9f983ae94d2e1e6866c34b3c87374a349631
The TX radio will normally transmit a late not-timed packet when an
underflow occurs between packets within a burst. However, if it was
only one cycle late, then the packet would be dropped. This change
rearms the state machine more quickly in this corner case to allow
this late packet to be accepted. The underflow error will still be
reported.
Original-commit: 9faac6597cf21ca11e40d4e98797cea2848c40b0
This Python utility was getting a bit rotten. The following updates
where made:
- Reformatted using ni-python-styleguide
- Fixed formatting of regex strings by declaring them 'raw'
- Updated docstrings and any linter issues
On Pyton 3.12 and beyond, this will no longer throw SyntaxError
warnings.
Original-commit: 0dede88c6535ae6ffb30b162c83dc01d59d3bfa0
Previously, the build tools for the FPGA bitfiles would try and
autodetect the Vivado executable, but would allow for a `vivado_lab`
executable. However, Vivado Lab Edition can't build bitfiles nor run
testbenches. Its only use with the USRP FPGA build tooling is to run
`viv_jtag_program` and `viv_jtag_list` (which are command-line proxies
for probing FPGAs attached to JTAG, and for programming bitfiles over
JTAG, e.g. to an X3x0).
When Vivado Lab and Vivado were present, it was possible that we ran
into issues where Vivado Labs would be preferred, and then builds or
testbenches would fail.
We therefore remove the ability to use Vivado Lab. Running the Vivado
Lab Edition with the GUI, and loading and probing bitfiles is of course
still possible, but tools like `rfnoc_image_builder` can no longer
accidentally try to use Vivado Lab instead of regular Vivado.
Original-commit: 21c4c591a51d520c7aac7108e853e59c4953f953
The tready signal that was used when EN_MAGNITUDE equals 0 was not
correct. This commit allows EN_MAGNITUDE to be disabled.
Original-commit: ef449523df61268d4efbc86a12cb098c2b2bf239
This replaces the legacy RFNoC FFT block with a new one of the same
name that includes a superset of the original features. New features
include cyclic prefix insertion or removal and FFT sizes up to 64k.
Original-commit: 25fffb006755b2e91f0138eb4af3ab9e16b8690c
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.
Original-commit: 0d3d69493aac9239ae437b04f291c61669678606
- Add documentation
- Add generate block labels
- Remove tabs and fix indentation
- Separate the code into three logical sections
Original-commit: 76074ecb319bf770805374b81c966b94cba898c5
This simplifies image core files by generating a RADIO_NIPC parameter
for the X410, X440 and E31x BSP files. The IO port widths for X410 are
now dynamically widened based on the NIPC value, which is a function of
the RF_BW parameter, and cannot be modified.
The radio block can now read the NIPC value from the BSP, and populate
its spc parameter dynamically. This avoids having to know the right spc
value when writing YAML image core files and reduces redundancy.
This also removes the RADIO_NIPC parameter entirely from all the image
core files. This parameter was fine, but it was a bit confusing because
it referenced a Verilog parameter, which you just had to know was there
in the generated Verilog. By referencing the BSP parameter instead, the
YAML files (BSP, radio.yml, and image core file) are now self-contained
regarding the RADIO_NIPC/spc information.
As a minor upside, the input wire widths for X410's and N310's
rfnoc_image_core.sv module are now generated with the correct widths,
and not, as before, with the worst-case width (and then we assume Vivado
will do the right thing).
Original-commit: 53b4d7a21018fe7aabf9f774260aefb41297a41b
Wade Fife