Wade Fife 82e1da1b78 fpga: lib: Cleanup axi_demux module ...

- Add documentation
- Add generate block labels
- Remove tabs and fix indentation
- Separate the code into three logical sections


Original-commit: 76074ecb319bf770805374b81c966b94cba898c5

2024-12-17 22:13:42 +01:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fpga: lib: Cleanup axi_demux module

2024-12-17 22:13:42 +01:00

sim

fpga: sim: Initialize test_status

2024-06-20 11:35:27 +02:00

tools

fpga: tools: Add JUnit XML support to run_testbenches

2024-12-11 09:08:11 +01:00

top

fpga: x4xx: assemble x410/x440-version-info.dtsi in BUILD_DIR

2024-11-22 08:00:03 +01:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

Description

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%