Wade Fife 4f99fee248 fpga: lib: Add complex_to_magphase_int17 IP ...

The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its
(X,Y) inputs and its magnitude output. So, having 17 bits means we have
enough precision to represent the entire range of an sc16. The 16-bit
CORDIC is insufficient to cover this entire range.


Original-commit: 0d3d69493aac9239ae437b04f291c61669678606

2024-12-17 22:13:42 +01:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

fpga: lib: Add complex_to_magphase_int17 IP

2024-12-17 22:13:42 +01:00

sim

fpga: sim: Initialize test_status

2024-06-20 11:35:27 +02:00

tools

fpga: tools: Add JUnit XML support to run_testbenches

2024-12-11 09:08:11 +01:00

top

fpga: x4xx: assemble x410/x440-version-info.dtsi in BUILD_DIR

2024-11-22 08:00:03 +01:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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