This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.
Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
Thange allows the mux to switch cleanly between packets, if the mux
select input is changed while a packet is in flight.
Original-commit: cee09d96aee51795ba2c6578f75f25f30ea11548
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.
Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.
Also cleans up trailing white space.
Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
The max FFT size was 4096, but we don't currently have any devices that
can do that without modification. This is because, currently, the FFT
size must be the same as the packet size, and the largest packet
size supported by most devices is about 8000 bytes, or 2000
sc16 samples. Therefore, the largest FFT size supported without
modifying other code is 1024 samples.
This change frees up about 21% of the LUTs and 36% of the BRAM used by
axi_fft and makes the software block controller and the IP agree on the
maximum FFT size.
Original-commit: 4f387c8ff0571deedc86dc459e94e555b9768282
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.
Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.
MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.
In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.
Original-commit: 0df2f9932cc270b8f1a705ea2543df8792005878
- Detect dropped words at the dispatch level. This prevents
an overflow on CHDR from block CPU.
- Dropped packets are recorded as CPU or CHDR drop count
- Refactor to put chdr_xport_adapter.sv in different clock
domain to improve timing
- Unwrinkle tkeep/trailing transitions
Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
This change fixes the case where CHDR_W < ITEM_W*NIPC.
It also adds a state machine to stall the input to the pyld_fifo to
ensure that the pkt_info_fifo will not overflow. Previously in some
cases it allowed the same word to be inserted into the pyld_fifo
multiple times.
Original-commit: b862eda69cf41c7044a1805324f2fcfef5b0ba3d
- Made some things optional to reduce logic when
used with the new xport_sv:
(1) Clocking to sys_clk
(2) Preamble insertion
- New options to CUTTHROUGH faster on the TX path.
The new xport_sv already has a gate to accumulate at
its clock crossing.
Original-commit: a68e7101167a4b5bf7b60ed90d963982aae735b8
This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that
can be used to stitch onto Verilog port_maps.
Original-commit: 6ef642e3ac44c52b98b124f30dc84b1683859989
This module takes an AXI-Stream without TLAST and outputs the
same AXI-Stream with TLAST based on the provided packet size
input.
Original-commit: b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
Contains a fix for the AXI4LITE_ASSIGN macro, and adds
AXI4LITE_PORT_ASSIGN, AXI4LITE_PORT_ASSIGN_NR, and
AXI4LITE_DEBUG_ASSIGN macros.
Original-commit: c718faf3387a07a9a1b86ab473f6ed7ac4cb493a
Components are connected together with AxiStreamIfc. Some features
include:
(1) Add bytes to the start of a packet
(2) Remove bytes from a packet
(3) Wrappers for some older components
a. fifo - buffer but imediately pass a packet
b. packet_gate - buffer and hold till end of packet
c. width_conv - cross clock domains and change width of axi bus
The AxiStreamIf was moved from PkgAxiStreamBfm to its own file. It can
be used to connect to ports with continuous assignment.
AxiStreamPacketIf must be used procedurally but allows the following
new methods:
- reached_packet_byte - notify when tdata contains a paritcular byte
- get_packet_byte/get_packet_field - extract a byte or field from axi
- put_packet_byte/put_packet_field - overwrite a byte or field onto axi
Original-commit: c3bca6c87700054c96320de119a58f6a688dbd5a
(1) Synthesizable AxiLiteIf
(2) Simulation model for AxiLite contains an AxiLiteTransaction class
and an AxiLiteBfm class.
Important Methods
a. wr - performs non-blocking write and checks for expected response
b. wr_block - performs a blocking write and provides response
c. rd - performs a non-blocking read and checks for expected response
d. rd_block - persforms a blocking read and provides response
The model allows parallel execution of reads and writes, but enforces
rd and write ordering when using the above methods. When transactions
are posted directly, ordering is not guaranteed, and reads and writes
are put on the interface immediately.
Original-commit: afee1888dd7c2d9d95e537f505ce7ab36252763a
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.
Used in xport when calculating new UDP headers for CHDR traffic.
Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.
Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
The existing SPI core (simple_spi_slave.v) was limited to 32 bit. This
commit adds a second spi core with capability to transfer up to 64 bits
while keeping the same amount of resources when using generic setting
MAX_BITS = 32. Furthermore, the new module aligns mosi and miso with the
edges of sclk. The register stages were not aligned in the existing
version.
Original-commit: 366cab1fef44f1132a2acf8046ecaeac80793ccc
Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.
Original-commit: 3f6ad749b06094b0e16b412a791ba3f2ac509600
Add DEFAULT_M and DEFAULT_N parameters for rate changing cores.
This allows the host to not need to configure fixed rate change
cores.
Original-commit: 983fad664436301c31c3bc8c81b538a41537598b
The decimation in the rx_frontend_gen3 was added to reduce the bandwidth
between the Radio and the DDC due to the limitation in bandwidth over
the crossbar for dynamically connected blocks. The default FPGA image
for the X300 now has a static connection between the Radio and DDC, so
this is no longer necessary.
This change allows the TwinRX receive channels to be time aligned with
channels from other daughterboards so they can be used in the same
streamer.
Signed-off-by: Michael West <michael.west@ettus.com>
Original-commit: d0c162bc7a4ac82f6104506b17d7be05e1780336
Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample. Defaults to legacy behavior.
Minor compat number bumped on DUC and DDC blocks.
Signed-off-by: Michael West <michael.west@ettus.com>
Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62
Wade Fife