miegl/b210-k7-fpga
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439c2af5e2b833855692d2251a53040b0498b528
b210-k7-fpga/lib
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Andrew Moch 439c2af5e2 fpga: lib: Add xge features for new xport_sv 
- Made some things optional to reduce logic when
   used with the new xport_sv:
   (1) Clocking to sys_clk
   (2) Preamble insertion
 - New options to CUTTHROUGH faster on the TX path.
   The new xport_sv already has a gate to accumulate at
   its clock crossing.


Original-commit: a68e7101167a4b5bf7b60ed90d963982aae735b8
2020-07-31 13:32:59 -05:00
..
axi
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
axi4lite_sv
fpga: lib: Update AxiLiteIf
2020-07-31 11:55:47 -05:00
axi4s_sv
fpga: lib: Add synthesizable AXI4-Stream SV components
2020-06-25 14:44:04 -05:00
control
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
control_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dsp
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00
extramfifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo
fpga: lib: Fix axi_packet_gate RAM dib width
2020-06-29 13:41:15 -05:00
fifo_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gpif2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hls
fpga: rfnoc: Add RFNoC Add/Sub block
2020-05-28 15:04:05 -05:00
io_cap_gen
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
io_port2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ip
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
packet_proc
fpga: lib: Pipeline and add clken to ip_hdr_checksum
2020-06-24 09:55:14 -05:00
packet_proc_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
radio_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
rfnoc
fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64
2020-07-30 15:28:35 -05:00
sim
fpga: rfnoc: Fix testbenches to run under ModelSim
2020-07-20 15:33:22 -05:00
simple_gemac
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing
fixup! lib: add option for output register in pps generator
2020-02-05 09:26:57 -06:00
vita_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
vivado_ipi
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wb_spi
fpga: lib: extend wb_spi ability to limit transmission length
2020-06-04 14:46:19 -05:00
white_rabbit/wr_cores_v4_2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wishbone
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge_interface
fpga: lib: Add xge features for new xport_sv
2020-07-31 13:32:59 -05:00
zpu
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zynq_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00