miegl/b210-k7-fpga
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cbe5e99e171944d56ecc955995e5cc0797632a85
b210-k7-fpga/lib
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Wade Fife cbe5e99e17 fpga: rfnoc: Add Log-Power block 
Original-commit: cf82b36388880237fe7b690c16dde46afc1a3da3
2020-06-29 14:03:17 -05:00
..
axi
fpga: lib: Add AXI-Stream splitter (axis_split)
2020-04-14 16:37:43 -05:00
axi4lite_sv
fpga: lib: Add features to axi_lite.vh
2020-06-26 10:36:37 -05:00
axi4s_sv
fpga: lib: Add synthesizable AXI4-Stream SV components
2020-06-25 14:44:04 -05:00
control
fpga: lib: add extended spi core for 64bit
2020-06-17 07:13:20 -05:00
control_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dsp
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00
extramfifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo
fpga: lib: Fix axi_packet_gate RAM dib width
2020-06-29 13:41:15 -05:00
fifo_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gpif2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
hls
fpga: rfnoc: Add RFNoC Add/Sub block
2020-05-28 15:04:05 -05:00
io_cap_gen
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
io_port2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ip
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
packet_proc
fpga: lib: Pipeline and add clken to ip_hdr_checksum
2020-06-24 09:55:14 -05:00
packet_proc_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
radio_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
rfnoc
fpga: rfnoc: Add Log-Power block
2020-06-29 14:03:17 -05:00
sim
fpga: lib: Pipeline and add clken to ip_hdr_checksum
2020-06-24 09:55:14 -05:00
simple_gemac
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing
fixup! lib: add option for output register in pps generator
2020-02-05 09:26:57 -06:00
vita_200
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
vivado_ipi
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wb_spi
fpga: lib: extend wb_spi ability to limit transmission length
2020-06-04 14:46:19 -05:00
white_rabbit/wr_cores_v4_2
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
wishbone
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xge_interface
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zpu
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
zynq_fifo
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00