This simplifies image core files by generating a RADIO_NIPC parameter
for the X410, X440 and E31x BSP files. The IO port widths for X410 are
now dynamically widened based on the NIPC value, which is a function of
the RF_BW parameter, and cannot be modified.
The radio block can now read the NIPC value from the BSP, and populate
its spc parameter dynamically. This avoids having to know the right spc
value when writing YAML image core files and reduces redundancy.
This also removes the RADIO_NIPC parameter entirely from all the image
core files. This parameter was fine, but it was a bit confusing because
it referenced a Verilog parameter, which you just had to know was there
in the generated Verilog. By referencing the BSP parameter instead, the
YAML files (BSP, radio.yml, and image core file) are now self-contained
regarding the RADIO_NIPC/spc information.
As a minor upside, the input wire widths for X410's and N310's
rfnoc_image_core.sv module are now generated with the correct widths,
and not, as before, with the worst-case width (and then we assume Vivado
will do the right thing).
Original-commit: 53b4d7a21018fe7aabf9f774260aefb41297a41b
... to support custom image core name, example:
rfnoc_image_builder -y n310_rfnoc_image_core.yml -n my_custom_name
The device tree source files were renamed to match the target
name used in the Makefile.
example:
old: dts/usrp_n310_fpga_hg.dts
new: dts/N310_HG.dts
The source file is used to compile the final .dts file in the BUILD_DIR.
example: build-my_custom_name/N310_HG.dts
The final .dts file is copied to the BUILD_OUTPUT_DIR as part of the
post build steps and renamed to the custom image core name.
example: build/my_custom_name.dts
This completes the change that was introduced with commit 2afc66f132.
Original-commit: d40db57f2e03c322ac6b0001e0a59d4a14a5a3b9
- All RFNoC capable targets now require rfnoc_image_builder to be built
- `make help` is updated for all targets to provide more useful and
up-to-date information
- The FPGA manual is also updated
- All checked-in build artifacts are now removed from git
- axi_ram_fifo.yml is updated to provide include path information
(required for building N3xx BIST images, which use this)
Original-commit: 28b994406d4c9547b1e2add62781b6a8162fdb74
Most important effect of this change: rfnoc_image_builder is now
required to build bitfiles, 'make' alone won't suffice any longer!
This is a huge changeset to the image builder that combines multiple new
features:
- There no longer is a separate edge file for the static router. The
static routes are generated as a Verilog parameter directly into the
rfnoc_core_kernel (which is also modified).
- image_builder.py is split up into several smaller files. Code is moved
into yaml_utils.py, and the new files grc.py, builder_config.py
- Generic module support is added. Aside from noc blocks and stream
endpoints, we can now instantiate arbitrary modules (they also require
a YAML description file).
- To enable such modules, resets are now also tracked the same way that
clock domains are.
- The ImageBuilderConfig config object now more closes matches the
original YAML file. The attributes 'clk_domain_con' and 'block_con' are
removed. Instead, the attributes 'connections' and 'clk_domains' are
sanitized and amended with extra annotations. The templates are
updated to reflect this change.
- IO ports can now carry parameters, e.g., to have variable wire widths
based on the configuration.
- Many Pylint warnings were resolved.
- Add inheritance support for image core YAML files.
This allows image core files to (recursively) inherit from other image
core files. To do so, simply put an 'inherit' entry at the top of the
file:
```yaml
inherit: 'x410_radio_base.yml'
```
- The inheritance feature is used as part of the image core files.
- Image core and DTS files are now generated as a build artefact into
the build directory. This requires the usage of rfnoc_image_builder to
build images. As a consequence, it is no longer required to check in
image core Verilog files.
- As another consequence, rfnoc_image_builder is required to build
bitfiles!
- Image flavours are no longer defined through Makefiles, but purely
from the image core YAML files.
- Remove all image core YAML files that do not generate a shipping
image. Because of the inheritance feature and the requirement to use
the image builder, it is trivial to add new YAML files.
- Add support for transport adapters through the YAML files. Before,
transport adapters were inferred from the make target (e.g.,
X410_X4_200 would have four 10GbE links based on the 'X4' substring).
Now, transport adapters are defined via the image core YAML.
- This feature is currently only used (or can be used) by the X4xx
series. Older devices may or may not be ported to allow custom
transport adapters in the future.
- Add parameters to the BSP YAMLs and the devices itself. This allows
setting global parameters in the image core files. For example, the
X4x0 devices use this to decide if they instantiate DRAM channels.
- DTS includes and constraint files can now be requested by
blocks/transport adapter through their YAML files. They do no longer
need to be listed in the Makefile.
- Support for secure image cores. These are image cores that allow
incorporating RFNoC blocks that require license keys and thus can't
live in an open-source environment. This solution adds the option for
secure image cores without touching the open source feature set.
- Add --reuse option to allow manual editing of generated artefacts
- Allow IO signatures from any module: until now IO signatures had to be
defined in a single file (io_signatures). This file will persist. In
addition each module can add its own IO signature as with the same
format the core IO signatures placed under the top level key
`io_signatures`. IO signatures are still maintained in a global
dictionary. The consequence is that they can be shared among
independent modules as well as they have to have a globally unique
name. The image builder will warn about detected name clashes for the
signatures.
- As a consequence, some less commonly used IO signatures were moved to
their corresponding module YAML files.
Co-authored-by: Wade Fife <wade.fife@ni.com>
Co-authored-by: Lars Amsel <lars.amsel@ni.com>
Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
The frontend synchronization upon time change was removed, but is
required to synchronize the RX frontend modules when sharing LOs on
TwinRX. This change restores the behavior.
Signed-off-by: michael-west <michael.west@ettus.com>
Original-commit: c70b479007ab9f578577dfb5c2de6660e877d9a3
Adds a BUILD_BASE_DIR makefile variable that allows you to specify the
base directory for FPGA build outputs. This allows you to put the
output from each run of make into a unique directory, or to run
multiple instances of make in parallel with each build's output being
put in a different directory. For example:
make X310_XG BUILD_BASE_DIR=/path/to/builds
Original-commit: bc6db8409ba756bbad0d0c158ffb00c614b58fd9
Adds a BUILD_SEED make variable that can be set to a 32-bit integer,
and adds an FPGA read-only register initialized by this variable.
Changing this variable will randomly affect the FPGA build results.
This can be useful when your build fails timing by a small amount,
allowing you to build again and get different results with the same
code.
For example, you could run the following to produce an FPGA build with
different timing results from the default build:
make X310_XG BUILD_SEED=123
Original-commit: 3a3a03486f9221c2e59fa6d0826c23d17730956d
Patch AR76780 was already listed as a requirement for X4xx and N3xx,
but was not listed as a requirement for X3xx and E3xx. This change
makes it required for all Vivado-based USRPs.
Original-commit: 5aa6bc4418a30d6e6fde80b80632f9f9115ea5c4
This adds the ability to do IP generation and FPGA builds using the
--jobs (-j) option with Make. For example, rather than generating each
IP one after another, you can generate up to N at a time using N Vivado
instances. This greatly reduces the IP generation time. Similarly,
parallel jobs can be used to easily build different FPGA variants
simultaneously.
Because FPGA builds can consume a lot of memory, care must be taken to
ensure that the number of jobs is not too high for the amount of memory
available.
New IP make targets were added for each USRP so that IP can be built
separately from the FPGA. The IP targets are now a dependency on each
FPGA target.
For example, you can generate the IP for X310 using 4 parallel jobs
using the following command:
make -j4 X310_IP
Or, build two X310 bitstreams simultaneously:
make -j2 X310_XG X310_HG
Original-commit: 4b03e237a96ee277eefff257d65b08708c38662c
This causes the latest RFNoC protocol version to be used by default
and avoids the need to update YAML files every time the RFNoC
protocol version gets bumped.
Original-commit: 92016a585a5223a9a7678134e318e412875b64c2
Update USRP RFNoC iamge core YAML files to use the more consistent
device port names. Clean up the formatting and make the files more
consistent.
Original-commit: 6318eaeff548f760056af7c8172937a296409d25
This updates all RFNoC devices so that they get the RFNoC protocol
version and CHDR width in the same way, from the output generated by
the RFNoC image builder.
Original-commit: 6f038dc2f69b38e715206b2e700fdd3a1bbc638e
Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.
Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3
This adds DRAM support to E31x devices. Due to the size of the DDR3
memory controller, it is not enabled by default. You can include the
memory controller IP in the build by adding the DRAM environment
variable to your build. For example:
DRAM=1 make E310_SG3
Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
This sets the ARCH and PART_ID environment variables so that the
selected part family is used for simulations by default. This can be
overridden by changing them in the Makefile for the testbench if a
testbench requires a specific part family. Prior to this change, the
default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which
required support for that part to be installed.
Original-commit: c176046dff4941bcec27b0b72e5a68264c4808e5
Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.
Original-commit: b0033158a4c520063540881451d8daac91e98714
Change version from a numeric to a string, in order to
differentiate between versions like "1.1" and "1.10".
Original-commit: ca21048bd2f832b20bb36763f76d46b861b697a5
This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This
makes the naming consistent with the rest of the build process (which
uses "e310" for all variants of e31x) and fixes an issue in which the
wrong file name was used by rfnoc_image_builder.
Original-commit: bbd43b16e18ef0a0311ddf4635cbd29c4ac3c367
Fixing an issue in which a very slow radio_clk (due to low sample clock
rate) could cause bus transactions to be issued to the timekeeper
faster than it could service them, resulting in a timeout. This change
replaces RegPort with CtrlPort so that proper flow control can be
maintained to the timekeeper.
Original-commit: 2e910c5307702c3f3efb6dc8cb60f4f71ce11e67
Device was set to e31x, but this is not a valid device type. All e31x
devices use the e310 device type.
Original-commit: 60b76ebb31f9d1672c1b18367346b3fb522e13e9
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
- Fixed some incorrect comments
- Fixed some missing wire declarations for internal NIC
- Fix wire declarations for GPIO (they were declared too late)
Original-commit: b18eaa75de2d1dcba2a1be0ee0b862a57e976cca
Xilinx changed the way [all_registers -edge_triggered] is treated such
that set_max_delay constraints that use it can cause segmentation and
cause clocks to not be propagated to all endpoints. Changing to
[all_ffs] avoids this potential issue.
Original-commit: 55e422535292c29de00b80f15b0a49ca3fb94f26
Martin Braun