miegl/b210-k7-fpga
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b2684c42a7a1131cf620e6724ce47f970b8eca81
b210-k7-fpga/top/e31x
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Wade Fife b2684c42a7 fpga: e31x: Fix DRAM traffic gen IP name 
Change name in DRAM IP Makefile from IP_MIG_7SERIES_TG_SRCS to
IP_DDR3_16BIT_TG_SRCS to match the naming of other variables.


Original-commit: febf339e0df412e54cf43a204c280128d8ca1ec3
2022-03-23 08:55:36 -05:00
..
dts
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
ip
fpga: e31x: Fix DRAM traffic gen IP name
2022-03-23 08:55:36 -05:00
sim
fpga: rfnoc: Fix testbenches to run under ModelSim
2020-07-20 15:33:22 -05:00
.gitignore
fpga: e31x: Add gitignore file
2020-07-18 13:33:42 -05:00
axi_pmu.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_e31x.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_core.v
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
e31x_dram.v
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
e31x_idle_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_idle.v
e31x: Swap out liberio for internal ethernet in the idle image
2020-07-18 11:52:58 -05:00
e31x_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_timing.xdc
fpga: e31x: Update constraints to avoid timing issues
2020-04-08 17:24:15 -05:00
e31x.v
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
e310_io.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e310_rfnoc_image_core.v
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
e310_rfnoc_image_core.vh
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
e310_rfnoc_image_core.yml
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
e310_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
Makefile.e31x.inc
fpga: e31x: Add DRAM support
2022-02-10 18:13:44 -07:00
ppsloop.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv.sh
fpga: Set default part for sim in setupenv.sh
2021-08-30 08:20:10 -05:00
spi_slave.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00