Wade Fife e659f0cfdd Fix instances of sim preamble ...

Original-commit: d6ba2dfb5cb524ba2116cb0c3613af9650e57d03

2024-09-17 08:43:22 -05:00

..

dts

fpga: e31x/e320/n3xx/x400: Rework device tree file generation

2024-09-13 08:44:30 -05:00

ip

fpga: e31x: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

sim

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

.gitignore

fpga: e31x: Add gitignore file

2020-07-18 13:33:42 -05:00

axi_pmu.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build_e31x.tcl

fpga: Add incremental to strategies for e3xx, n3xx, x3xx

2024-03-14 16:35:11 -05:00

e31x_core.v

FPGA: Synchronize X300 RX frontends on time change

2023-05-10 14:22:42 -05:00

e31x_dram.v

fpga: e31x: Add DRAM support

2022-02-10 18:13:44 -07:00

e31x_idle_pins.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_idle.v

e31x: Swap out liberio for internal ethernet in the idle image

2020-07-18 11:52:58 -05:00

e31x_pins.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_timing.xdc

fpga: e31x: Update constraints to avoid timing issues

2020-04-08 17:24:15 -05:00

e31x.v

fpga: e31x: Cleanup MTU parameters

2022-09-01 14:41:55 -05:00

e310_io.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e310_rfnoc_image_core.yml

fpga: Align build process for all targets

2024-06-11 10:20:08 +02:00

Makefile

fpga: e31x/e320/n3xx/x400: Rework device tree file generation

2024-09-13 08:44:30 -05:00

Makefile.e31x.inc

fpga: Put dependencies first in Makefile SRCS list

2024-09-06 17:58:33 -05:00

ppsloop.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

setupenv.sh

fpga: Require AR76780 for X3xx and E3xx

2022-09-23 15:09:35 -05:00

spi_slave.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00