Wade Fife e659f0cfdd Fix instances of sim preamble ...

Original-commit: d6ba2dfb5cb524ba2116cb0c3613af9650e57d03

2024-09-17 08:43:22 -05:00

export/x300/radio

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

lib

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

sim

fpga: sim: Initialize test_status

2024-06-20 11:35:27 +02:00

tools

fpga: ci: remove color coding from FPGA bitfile name

2024-07-11 15:29:53 +02:00

top

Fix instances of sim preamble

2024-09-17 08:43:22 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

S

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84 MiB

Languages

Verilog 42.5%

VHDL 13%

SystemVerilog 12%

HTML 11.1%

C 9.6%

Other 11.6%