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2f517134cd50b8d47d784c42d7d3c83e6cdaad3f
b210-k7-fpga/top/e31x
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Martin Braun 2f517134cd fpga: e31x: Add gitignore file 
Original-commit: dc32aa5cd4fb174ee3c616f854f499a53137aa75
2020-07-18 13:33:42 -05:00
..
dts
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
ip
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
sim
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
.gitignore
fpga: e31x: Add gitignore file
2020-07-18 13:33:42 -05:00
axi_pmu.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_e31x.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_core.v
e31x: Minor cleanup on top-level e31x.v module
2020-07-18 13:33:42 -05:00
e31x_idle_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_idle.v
e31x: Swap out liberio for internal ethernet in the idle image
2020-07-18 11:52:58 -05:00
e31x_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_rfnoc_image_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_rfnoc_image_core.yml
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e31x_timing.xdc
fpga: e31x: Update constraints to avoid timing issues
2020-04-08 17:24:15 -05:00
e31x.v
e31x: Minor cleanup on top-level e31x.v module
2020-07-18 13:33:42 -05:00
e310_io.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e310_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.e31x.inc
e31x: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
ppsloop.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
spi_slave.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00