This changes the behavior of the stream command with the INIT OpCode
such that sending the command with 0 for the values causes no flow
control stream status packets to be sent in response to incoming data.
Original-commit: 7c849afec4dad605ff6f32f7319933f99a4cd1ce
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.
Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
This change prevents packets from being chopped midway if the
switchboard configuration is changed when a packet is in flight.
Original-commit: f2ec5c91a79cee4c05465349d7e0da865ad1bead
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.
Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.
Also cleans up trailing white space.
Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
This adds additional tests to the testbench to cover register reads and
basic IFFT functionaltiy.
Original-commit: 9157e11795f3ca86dae2ee930e60a79470d1447f
This commit derives parameters for MAX10 devices if provided by the
DEVICE parameter.
MAX10 devices FIFO generator support up to 36 bit wide FIFOs using
embedded memory (M9K) in simple dual port mode, which is treated
equally to RAM in the parameters.
In combination with sorting the ctrlport signals by usage, the used
resources can be reduced on the MAX10 devices from 6 to 3 M9K blocks
for a ctrlport_clk_cross instance without time and portids.
Original-commit: 0df2f9932cc270b8f1a705ea2543df8792005878
- Detect dropped words at the dispatch level. This prevents
an overflow on CHDR from block CPU.
- Dropped packets are recorded as CPU or CHDR drop count
- Refactor to put chdr_xport_adapter.sv in different clock
domain to improve timing
- Unwrinkle tkeep/trailing transitions
Original-commit: 7f86724ec3387f75d39d683b2ac5f5152e714c74
Adding a check for bursts that cross the 4 KiB boundary to the AXI4
memory model. Crossing a 4 KiB boundary is not allowed by AXI4.
Original-commit: 24f8bb39fd2769ff93d11b21152a834500152de4
This change fixes the case where CHDR_W < ITEM_W*NIPC.
It also adds a state machine to stall the input to the pyld_fifo to
ensure that the pkt_info_fifo will not overflow. Previously in some
cases it allowed the same word to be inserted into the pyld_fifo
multiple times.
Original-commit: b862eda69cf41c7044a1805324f2fcfef5b0ba3d
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.
Used in xport when calculating new UDP headers for CHDR traffic.
Original-commit: dd9847c5c3c3fac17658b526a7d8894711af086e
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.
Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
Add DEFAULT_M and DEFAULT_N parameters for rate changing cores.
This allows the host to not need to configure fixed rate change
cores.
Original-commit: 983fad664436301c31c3bc8c81b538a41537598b
The decimation in the rx_frontend_gen3 was added to reduce the bandwidth
between the Radio and the DDC due to the limitation in bandwidth over
the crossbar for dynamically connected blocks. The default FPGA image
for the X300 now has a static connection between the Radio and DDC, so
this is no longer necessary.
This change allows the TwinRX receive channels to be time aligned with
channels from other daughterboards so they can be used in the same
streamer.
Signed-off-by: Michael West <michael.west@ettus.com>
Original-commit: d0c162bc7a4ac82f6104506b17d7be05e1780336
Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample. Defaults to legacy behavior.
Minor compat number bumped on DUC and DDC blocks.
Signed-off-by: Michael West <michael.west@ettus.com>
Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62
The axis_data_to_chdr block previously only sampled the sideband
information at the end of the packet. This adds a parameter that
controls if the sideband information should be sampled at the beginning
of the packet or the end of the packet. In the former case, large
internal packet buffers are not required.
Original-commit: a8c4f021277cf3b0a0897fa9da0252541512f3a6
The latency through the combiner is static if only one master interface
is used and PRIORITY=1 is set.
Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7
This adds variants of the send and recv methods in RfnocBlockCtrlBfm
and ChdrIfaceBfm that input/output items instead of CHDR words.
Original-commit: aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6
This replaces chdr_word_t, which was a statically defined 64-bit data
type, with a paramaterizable data type that matches the defined CHDR_W.
Code that formerly referenced the chdr_word_t data type can now define
the data type for their desired CHDR_W and ITEM_W as follows:
// Define the CHDR word and item/sample data types
typedef ChdrData #(CHDR_W, ITEM_W)::chdr_word_t chdr_word_t;
typedef ChdrData #(CHDR_W, ITEM_W)::item_t item_t;
ITEM_W is optional when defining chdr_word_t if items are not
needed. Static methods in the ChdrData class also provide the ability to
convert between CHDR words and data items. For example:
// Convert CHDR data buffer to a buffer of samples
samples = ChdrData#(CHDR_W, ITEM_W)::chdr_to_item(data);
Original-commit: fc895feacb8dde3b02c9a4eccb4b4f4a654f2881
This changes the for loop to use the generate keyword, making it
compatible with Verilog 2001. This allows tools that only support
Verilog 2001 to use this file (e.g., Intel Quartus).
Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a
This eliminates the complicated semaphore from the testbench and brings
the radio testbench in line with the other testbenches.
Original-commit: 8727642de2aa22e982e012d85d32325f664a3e9e
Wade Fife