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Wade Fife 34d68cf4ca fpga: rfnoc: Add option to sample sideband info at start of packet 
The axis_data_to_chdr block previously only sampled the sideband
information at the end of the packet. This adds a parameter that
controls if the sideband information should be sampled at the beginning
of the packet or the end of the packet. In the former case, large
internal packet buffers are not required.


Original-commit: a8c4f021277cf3b0a0897fa9da0252541512f3a6
2020-04-14 16:37:43 -05:00
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blocks
sim: Add item support to RFNoC simulation
2020-03-09 13:43:05 -05:00
core
fpga: rfnoc: Add option to sample sideband info at start of packet
2020-04-14 16:37:43 -05:00
crossbar
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fosphor
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sim
sim: Parameterize chdr_word_t data type
2020-03-09 13:43:05 -05:00
utils
fpga: rfnoc: Add gate to dynamically enable control-port interfaces
2020-04-01 11:02:16 -05:00
xport
rfnoc: Add management filter to generic xport
2020-02-19 13:27:16 -06:00
.gitignore
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addsub.v
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addsub.vhd
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file_source.v
fpga: Fix errors found by linting with vsim
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fir_filter_slice.v
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Makefile.srcs
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