miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
855618402533667371dea1f49e87d1b2aee84c29
b210-k7-fpga/lib/rfnoc
T
History
Michael West 8556184025 TwinRX: Remove decimation from frontend 
The decimation in the rx_frontend_gen3 was added to reduce the bandwidth
between the Radio and the DDC due to the limitation in bandwidth over
the crossbar for dynamically connected blocks.  The default FPGA image
for the X300 now has a static connection between the Radio and DDC, so
this is no longer necessary.

This change allows the TwinRX receive channels to be time aligned with
channels from other daughterboards so they can be used in the same
streamer.

Signed-off-by: Michael West <michael.west@ettus.com>


Original-commit: d0c162bc7a4ac82f6104506b17d7be05e1780336
2020-05-12 12:03:31 -05:00
..
blocks
TwinRX: Remove decimation from frontend
2020-05-12 12:03:31 -05:00
core
fpga: Change default MTU to 10
2020-05-11 09:06:03 -05:00
crossbar
fpga: Change default MTU to 10
2020-05-11 09:06:03 -05:00
fosphor
rfnoc: Add RFNoC fosphor block
2020-04-14 16:37:43 -05:00
sim
sim: Parameterize chdr_word_t data type
2020-03-09 13:43:05 -05:00
utils
fpga: rfnoc: Add gate to dynamically enable control-port interfaces
2020-04-01 11:02:16 -05:00
xport
rfnoc: Add management filter to generic xport
2020-02-19 13:27:16 -06:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
addsub.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
addsub.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_async_stream.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_bit_reduce.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip_unsigned.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_deserializer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_drop_partial_packet.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fir_filter_dec.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fir_filter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_join.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_packer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_packet_mux.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_pipe_join.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_pipe_mac.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_pipe.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_rate_change.v
DUC/DDC: Add variable time increment
2020-05-12 12:03:31 -05:00
axi_repeat.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_and_clip_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_and_clip.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_round.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_serializer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_sync.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_tag_time.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_wrapper.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cadd.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_deframer_2clk.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_deframer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_fifo_large.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_framer_2clk.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_framer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_pkt_types.vh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_decimate.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cic_interpolate.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cmul.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
complex_invert.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
complex_to_mag_approx.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
complex_to_magsq.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
conj.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
const_sreg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
const.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
counter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_decoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_encoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_modify.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
cvita_hdr_parser.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
data_types.vh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
datapath_gatekeeper.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ddc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dds_freq_tune.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dds_timed.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
delay_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
delay_type2.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
delay_type3.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
delay_type4.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
duc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fft_shift.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
file_sink.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
join_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
keep_one_in_n.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
moving_sum.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult_add_rc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult_add.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult_rc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mult.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
multiply.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
noc_shell_regs.vh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
noc_traffic_counter.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
null_source.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
packet_resizer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
periodic_framer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
phase_accum.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ram_to_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_complex.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_stream_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
split_stream.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
vector_iir.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00