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Max Köhler ec70691e84 fpga: lib: add handshake to replace FIFO for ctrlport CDC 
The clock crossing of the ctrlport used FIFOs to transfer requests and responses
between clock domains. This commit adds a handshake based on the pulse
synchronizer to reduce the resource usage for ctrlport clock domain crossing.
Data is stored in a single register while the pulse synchronizer handles the
signaling of valid flags.


Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
2020-08-13 07:46:14 -05:00
..
blocks
fpga: rfnoc: Add tests to FFT block
2020-08-10 09:58:02 -05:00
core
fpga: rfnoc: Fix clock crossing in axis_data_to_chdr
2020-08-12 13:56:13 -05:00
crossbar
fpga: rfnoc: Add support for 512-bit CHDR widths
2020-06-18 09:09:34 -05:00
fosphor
rfnoc: Add RFNoC fosphor block
2020-04-14 16:37:43 -05:00
sim
fpga: rfnoc: Add support for 512-bit CHDR widths
2020-06-18 09:09:34 -05:00
utils
fpga: lib: add handshake to replace FIFO for ctrlport CDC
2020-08-13 07:46:14 -05:00
xport
fpga: remove liberio
2020-07-20 16:01:03 -05:00
xport_sv
fpga: lib: Update xport_sv
2020-08-05 17:18:12 -05:00
.gitignore
Merge FPGA repository back into UHD repository
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addsub.v
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addsub.vhd
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axi_async_stream.v
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axi_bit_reduce.v
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axi_clip_complex.v
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axi_clip_unsigned.v
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axi_clip.v
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axi_deserializer.v
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axi_drop_partial_packet.v
fpga: rfnoc: Add defaults for rate changing
2020-05-28 15:12:20 -05:00
axi_fir_filter_dec.v
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axi_fir_filter.v
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axi_join.v
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axi_packer.v
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axi_packet_mux.v
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axi_pipe_join.v
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axi_pipe_mac.v
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axi_pipe.v
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axi_rate_change.v
fpga: rfnoc: Add defaults for rate changing
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axi_repeat.v
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axi_round_and_clip_complex.v
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axi_round_and_clip.v
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axi_round_complex.v
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axi_round.v
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axi_serializer.v
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axi_sync.v
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axi_tag_time.v
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axi_wrapper.v
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cadd.v
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chdr_deframer_2clk.v
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chdr_deframer.v
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chdr_fifo_large.v
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chdr_framer_2clk.v
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chdr_framer.v
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chdr_pkt_types.vh
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cic_decimate.v
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cic_interpolate.v
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cmul.v
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complex_invert.v
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complex_to_mag_approx.v
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complex_to_magsq.v
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conj.v
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const_sreg.v
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const.v
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counter.v
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cvita_hdr_decoder.v
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cvita_hdr_encoder.v
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cvita_hdr_modify.v
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cvita_hdr_parser.v
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data_types.vh
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datapath_gatekeeper.v
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ddc.v
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dds_freq_tune.v
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dds_timed.v
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delay_fifo.v
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delay_type2.v
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delay_type3.v
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delay_type4.v
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duc.v
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fft_shift.v
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file_sink.v
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file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
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join_complex.v
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keep_one_in_n.v
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Makefile.srcs
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
moving_sum.v
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mult_add_rc.v
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mult_add.v
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mult_rc.v
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mult.v
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multiply.v
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noc_shell_regs.vh
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noc_traffic_counter.v
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null_source.v
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packet_resizer.v
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periodic_framer.v
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phase_accum.v
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ram_to_fifo.v
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sine_tone.v
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
split_complex.v
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split_stream_fifo.v
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split_stream.v
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vector_iir.v
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00