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Max Köhler 794e094218 fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1 
The latency through the combiner is static if only one master interface
is used and PRIORITY=1 is set.


Original-commit: 4e3650c0d7ac9bea3720151fbb23591f187590c7
2020-04-01 11:02:16 -05:00
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blocks
sim: Add item support to RFNoC simulation
2020-03-09 13:43:05 -05:00
core
Merge FPGA repository back into UHD repository
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crossbar
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fosphor
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sim
sim: Parameterize chdr_word_t data type
2020-03-09 13:43:05 -05:00
utils
fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1
2020-04-01 11:02:16 -05:00
xport
rfnoc: Add management filter to generic xport
2020-02-19 13:27:16 -06:00
.gitignore
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addsub.v
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addsub.vhd
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axi_async_stream.v
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axi_bit_reduce.v
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axi_clip_complex.v
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axi_clip_unsigned.v
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axi_clip.v
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axi_deserializer.v
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axi_drop_partial_packet.v
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axi_fir_filter_dec.v
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axi_fir_filter.v
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axi_join.v
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axi_packer.v
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axi_packet_mux.v
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axi_pipe_join.v
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axi_pipe_mac.v
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axi_pipe.v
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axi_rate_change.v
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axi_repeat.v
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axi_round_and_clip_complex.v
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axi_round_and_clip.v
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axi_round_complex.v
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axi_round.v
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axi_serializer.v
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axi_sync.v
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axi_tag_time.v
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axi_wrapper.v
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cadd.v
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chdr_deframer_2clk.v
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chdr_deframer.v
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chdr_fifo_large.v
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chdr_framer_2clk.v
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chdr_framer.v
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chdr_pkt_types.vh
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cic_decimate.v
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cic_interpolate.v
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cmul.v
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complex_invert.v
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complex_to_mag_approx.v
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complex_to_magsq.v
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conj.v
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const_sreg.v
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const.v
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counter.v
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cvita_hdr_decoder.v
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cvita_hdr_encoder.v
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cvita_hdr_modify.v
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cvita_hdr_parser.v
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data_types.vh
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datapath_gatekeeper.v
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ddc.v
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dds_freq_tune.v
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dds_timed.v
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delay_fifo.v
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duc.v
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fft_shift.v
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file_sink.v
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file_source.v
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
fir_filter_slice.v
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join_complex.v
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keep_one_in_n.v
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Makefile.srcs
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moving_sum.v
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mult_add_rc.v
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mult_add.v
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mult_rc.v
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mult.v
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multiply.v
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noc_shell_regs.vh
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noc_traffic_counter.v
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null_source.v
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packet_resizer.v
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periodic_framer.v
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phase_accum.v
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ram_to_fifo.v
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split_complex.v
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split_stream_fifo.v
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split_stream.v
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vector_iir.v
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